JPS6423564U - - Google Patents
Info
- Publication number
- JPS6423564U JPS6423564U JP11864287U JP11864287U JPS6423564U JP S6423564 U JPS6423564 U JP S6423564U JP 11864287 U JP11864287 U JP 11864287U JP 11864287 U JP11864287 U JP 11864287U JP S6423564 U JPS6423564 U JP S6423564U
- Authority
- JP
- Japan
- Prior art keywords
- lock
- wire
- locked
- lock body
- locked object
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000037431 insertion Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Landscapes
- Flexible Shafts (AREA)
- Lock And Its Accessories (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987118642U JPH0533645Y2 (en:Method) | 1987-07-31 | 1987-07-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987118642U JPH0533645Y2 (en:Method) | 1987-07-31 | 1987-07-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6423564U true JPS6423564U (en:Method) | 1989-02-08 |
| JPH0533645Y2 JPH0533645Y2 (en:Method) | 1993-08-26 |
Family
ID=31363165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987118642U Expired - Lifetime JPH0533645Y2 (en:Method) | 1987-07-31 | 1987-07-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0533645Y2 (en:Method) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7843068B2 (en) | 2005-06-30 | 2010-11-30 | Shinko Electric Industries Co., Ltd. | Semiconductor chip and method of manufacturing the same |
| US7875552B2 (en) | 2008-06-10 | 2011-01-25 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit chips having vertically extended through-substrate vias therein and chips formed thereby |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55166873U (en:Method) * | 1979-05-21 | 1980-12-01 |
-
1987
- 1987-07-31 JP JP1987118642U patent/JPH0533645Y2/ja not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55166873U (en:Method) * | 1979-05-21 | 1980-12-01 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7843068B2 (en) | 2005-06-30 | 2010-11-30 | Shinko Electric Industries Co., Ltd. | Semiconductor chip and method of manufacturing the same |
| US7875552B2 (en) | 2008-06-10 | 2011-01-25 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit chips having vertically extended through-substrate vias therein and chips formed thereby |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0533645Y2 (en:Method) | 1993-08-26 |