JPS6421503A - Operation instruction receiving circuit for video tape recorder - Google Patents

Operation instruction receiving circuit for video tape recorder

Info

Publication number
JPS6421503A
JPS6421503A JP62178255A JP17825587A JPS6421503A JP S6421503 A JPS6421503 A JP S6421503A JP 62178255 A JP62178255 A JP 62178255A JP 17825587 A JP17825587 A JP 17825587A JP S6421503 A JPS6421503 A JP S6421503A
Authority
JP
Japan
Prior art keywords
operation instruction
signal
waveform
period
instruction signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62178255A
Other languages
Japanese (ja)
Inventor
Hirofumi Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62178255A priority Critical patent/JPS6421503A/en
Publication of JPS6421503A publication Critical patent/JPS6421503A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce wiring for an operation instruction signal by converting signals with different periods respectively into digital signals '0' and '1'. CONSTITUTION:A converting operation instruction signal 1 is outputted as a digital signal '1' when the period of a waveform inputted within a fixed time T is one period, and when the period is 1.5 periods, outputted as '0'. A waveform obtained by delaying the signal 1 by time T through a delay circuit 3 and the waveform of the signal 1 itself are inputted to an EXOR 4, its output waveform is amplified by an amplifier 6, its high frequency component is removed through a low-pass filter, and the signal 1 is reversely converted into digital signals '0', '1' by a comparator 8. The output waveform of the comparator 8 is read in a shift register 10 to obtain an operation instruction output 11. Consequently, only one operation instruction signal can be obtained, so that the number of terminals of a semiconductor integrated device can be reduced and the number of wires for the operation instruction signal can be also reduced.
JP62178255A 1987-07-16 1987-07-16 Operation instruction receiving circuit for video tape recorder Pending JPS6421503A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62178255A JPS6421503A (en) 1987-07-16 1987-07-16 Operation instruction receiving circuit for video tape recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62178255A JPS6421503A (en) 1987-07-16 1987-07-16 Operation instruction receiving circuit for video tape recorder

Publications (1)

Publication Number Publication Date
JPS6421503A true JPS6421503A (en) 1989-01-24

Family

ID=16045295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62178255A Pending JPS6421503A (en) 1987-07-16 1987-07-16 Operation instruction receiving circuit for video tape recorder

Country Status (1)

Country Link
JP (1) JPS6421503A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483329A (en) * 1993-08-24 1996-01-09 Hitachi Metals, Ltd. Carrier for developer and method of electrophotographically forming visual image using same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483329A (en) * 1993-08-24 1996-01-09 Hitachi Metals, Ltd. Carrier for developer and method of electrophotographically forming visual image using same

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