JPS642116A - External setting system for electronic equipment - Google Patents

External setting system for electronic equipment

Info

Publication number
JPS642116A
JPS642116A JP62158374A JP15837487A JPS642116A JP S642116 A JPS642116 A JP S642116A JP 62158374 A JP62158374 A JP 62158374A JP 15837487 A JP15837487 A JP 15837487A JP S642116 A JPS642116 A JP S642116A
Authority
JP
Japan
Prior art keywords
setting
display
graphic
character
meaning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62158374A
Other languages
Japanese (ja)
Other versions
JPH012116A (en
JP2911001B2 (en
Inventor
Jiro Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP62158374A priority Critical patent/JP2911001B2/en
Publication of JPS642116A publication Critical patent/JPS642116A/en
Publication of JPH012116A publication Critical patent/JPH012116A/en
Application granted granted Critical
Publication of JP2911001B2 publication Critical patent/JP2911001B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Input From Keyboards Or The Like (AREA)
  • Position Input By Displaying (AREA)

Abstract

PURPOSE: To immediately recognize a set state by performing the display of the meaning of key input corresponding to the sequence of setting or change, or of the guide or the setting state of the next picture in a character or a graphic.
CONSTITUTION: A CPU 4 for setting performs the transfer of data with a program ROM 5 and a picture data ROM 6, and makes a display part 2 display the character or the graphic corresponding to the input of a switch via a graphic display processor 7. At this time, a loadable and erasable EEPROM 10 is used as a memory in which data is set or changed by the operation of the switch. And it is possible to display the meaning of the key input corresponding to the sequence of the setting or the change, and the guide or the setting state of the next picture in the character or the graphic. In such a way, since original meaning is displayed as it is, the setting is performed easily, and no operation manual, etc., is required, and mis-setting can be evaded.
COPYRIGHT: (C)1989,JPO&Japio
JP62158374A 1987-06-25 1987-06-25 External setting method for electronic devices Expired - Lifetime JP2911001B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62158374A JP2911001B2 (en) 1987-06-25 1987-06-25 External setting method for electronic devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62158374A JP2911001B2 (en) 1987-06-25 1987-06-25 External setting method for electronic devices

Publications (3)

Publication Number Publication Date
JPS642116A true JPS642116A (en) 1989-01-06
JPH012116A JPH012116A (en) 1989-01-06
JP2911001B2 JP2911001B2 (en) 1999-06-23

Family

ID=15670307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62158374A Expired - Lifetime JP2911001B2 (en) 1987-06-25 1987-06-25 External setting method for electronic devices

Country Status (1)

Country Link
JP (1) JP2911001B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58130490A (en) * 1982-01-29 1983-08-03 Nec Corp Store controlling circuit of non-volatile random access memory
JPS59115382U (en) * 1983-01-25 1984-08-03 株式会社建築設備設計研究所 schedule controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58130490A (en) * 1982-01-29 1983-08-03 Nec Corp Store controlling circuit of non-volatile random access memory
JPS59115382U (en) * 1983-01-25 1984-08-03 株式会社建築設備設計研究所 schedule controller

Also Published As

Publication number Publication date
JP2911001B2 (en) 1999-06-23

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