JPS6420727U - - Google Patents

Info

Publication number
JPS6420727U
JPS6420727U JP1987114866U JP11486687U JPS6420727U JP S6420727 U JPS6420727 U JP S6420727U JP 1987114866 U JP1987114866 U JP 1987114866U JP 11486687 U JP11486687 U JP 11486687U JP S6420727 U JPS6420727 U JP S6420727U
Authority
JP
Japan
Prior art keywords
semiconductor chip
ceramic package
metal pedestal
cavity
storing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987114866U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0621237Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987114866U priority Critical patent/JPH0621237Y2/ja
Publication of JPS6420727U publication Critical patent/JPS6420727U/ja
Application granted granted Critical
Publication of JPH0621237Y2 publication Critical patent/JPH0621237Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
JP1987114866U 1987-07-27 1987-07-27 セラミツクパツケ−ジ Expired - Lifetime JPH0621237Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987114866U JPH0621237Y2 (ja) 1987-07-27 1987-07-27 セラミツクパツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987114866U JPH0621237Y2 (ja) 1987-07-27 1987-07-27 セラミツクパツケ−ジ

Publications (2)

Publication Number Publication Date
JPS6420727U true JPS6420727U (US20030157376A1-20030821-M00001.png) 1989-02-01
JPH0621237Y2 JPH0621237Y2 (ja) 1994-06-01

Family

ID=31356000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987114866U Expired - Lifetime JPH0621237Y2 (ja) 1987-07-27 1987-07-27 セラミツクパツケ−ジ

Country Status (1)

Country Link
JP (1) JPH0621237Y2 (US20030157376A1-20030821-M00001.png)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57111050A (en) * 1980-12-26 1982-07-10 Fujitsu Ltd Semiconductor device
JPS5833860A (ja) * 1981-08-10 1983-02-28 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション 熱的ブリッジ素子
JPS6183041U (US20030157376A1-20030821-M00001.png) * 1984-11-07 1986-06-02

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57111050A (en) * 1980-12-26 1982-07-10 Fujitsu Ltd Semiconductor device
JPS5833860A (ja) * 1981-08-10 1983-02-28 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション 熱的ブリッジ素子
JPS6183041U (US20030157376A1-20030821-M00001.png) * 1984-11-07 1986-06-02

Also Published As

Publication number Publication date
JPH0621237Y2 (ja) 1994-06-01

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