JPS6419893A - High-speed switching circuit - Google Patents

High-speed switching circuit

Info

Publication number
JPS6419893A
JPS6419893A JP17673487A JP17673487A JPS6419893A JP S6419893 A JPS6419893 A JP S6419893A JP 17673487 A JP17673487 A JP 17673487A JP 17673487 A JP17673487 A JP 17673487A JP S6419893 A JPS6419893 A JP S6419893A
Authority
JP
Japan
Prior art keywords
unit switch
network
loads
switch
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17673487A
Other languages
Japanese (ja)
Other versions
JP2535928B2 (en
Inventor
Ryozo Kishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62176734A priority Critical patent/JP2535928B2/en
Publication of JPS6419893A publication Critical patent/JPS6419893A/en
Application granted granted Critical
Publication of JP2535928B2 publication Critical patent/JP2535928B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To improve the throughput with a high-speed switching circuit by dividing a Benes network into a distribution network (first half) and a routing network (second half) to distribute a input packet into the minimum value loads within the distribution network and monitoring the load of the middle unit switch of the Benes network to return the information on those loads to an input unit switch via a return signal line. CONSTITUTION:When a route is set for the packet which is newly inputted to a unit switch of the 0-th stage, the loads of two output terminals of said unit switch are compared with each other. In this case, the loads Q00 and Q01 connected to the output ports 1 and 2 are distributed at random as long as Q00=Q01 is satisfied and then outputted to the port 2 in the case of Q00>Q01 respectively. As a result, each unit switch always replaces the load information held presently by its follower connection unit switch. For the middle connection switch of a Benes network, '-1' is fed back to a unit switch of the 2nd stage as the load differential information on said connection switch when the packets are sent to a routing network. Thus the excellent throughput is obtained in terms of the average delay time characteristics, etc.
JP62176734A 1987-07-15 1987-07-15 High speed switching circuit Expired - Fee Related JP2535928B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62176734A JP2535928B2 (en) 1987-07-15 1987-07-15 High speed switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62176734A JP2535928B2 (en) 1987-07-15 1987-07-15 High speed switching circuit

Publications (2)

Publication Number Publication Date
JPS6419893A true JPS6419893A (en) 1989-01-23
JP2535928B2 JP2535928B2 (en) 1996-09-18

Family

ID=16018856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62176734A Expired - Fee Related JP2535928B2 (en) 1987-07-15 1987-07-15 High speed switching circuit

Country Status (1)

Country Link
JP (1) JP2535928B2 (en)

Also Published As

Publication number Publication date
JP2535928B2 (en) 1996-09-18

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