JP2535928B2 - High speed switching circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-speed switching circuit, and relates to a circuit for switching signals at high speed in a network that uniformly handles all multimedia such as voice, data, and moving images. It is a thing.

[Conventional technology]

Since a multistage switching circuit can form a large-scale switch circuit with a smaller amount of hardware than a crossbar switch, much research has been done in the research fields of switching networks and parallel computers. Conventionally, multistage switching circuits are roughly divided into two. One is a synchronous relocation-type non-blocking network, and the other is an asynchronous blocking network.

This time, the target multi-stage switching network is an asynchronous self-routing multi-stage switching circuit, which may be used for burst multiplexing node processing in burst transmission networks and parallel processing of signal processing. When processing high-speed packets that are input asynchronously, such as high-speed packet switching, it is important to use a method that does not require relocation processing when setting a route. Conventionally, as a non-synchronous multi-stage switching circuit, Banyan network (reference: J. Kalzel "Statistical Switching Architecture for Future Service" (J. Kulzer, "Sta
tistical Switching Architecture for Future Service
s ", ISS′84)) and a randomly distributed Benes network (reference: JS Turner,“ New Directions in Communica ”)
tions ", Zurich Seminar on Broadband Communications,
1986) has been proposed.

[Problems to be solved by the invention]

The Banyan network has a problem that internal congestion is likely to occur. Further, in the above-mentioned randomly distributed Benes network, in order to improve throughput as compared with the Banyan network,
Input packets were randomly distributed in the first half of the Benes network, and self-routed in the second half of the Benes network. However, in this method, since the input packets are randomly distributed, there is a limit in improving the throughput.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a high-speed switching circuit that switches signals at high speed and improves throughput in a network that handles all multimedia such as voice, data, and moving images in a unified manner. To provide.

[Means for solving problems]

In order to solve the above problems, the high-speed switching circuit of the present invention uses an input N-input N-output (N: natural number) Benes network composed of (2log ₂ N−1) -stage ₂ -input 2-output unit switches. Side unit switch is the 0th stage, output side unit switch is the (2log ₂ N-1) stage unit switch,
In addition, this Benes network is a multi-stage switching circuit composed of a distributed network in the first half and a routing network in the second half, the unit switch in the middle is a connection switch, and in the routing network, the input signal is a packet header with an output terminal number expressed in binary. In the distributed network, the load of the two output ports of the unit switch of the 0th stage is compared when the route of the packet newly input to the unit switch of the 0th stage is compared by the distributed network. When there is a large or small load, it outputs to the port with a small load, and the unit switch of the i-th stage (1 ≤ i ≤ log ₂ N-1)
The load information accumulated in the subordinate connection switches in the distribution network is compared with the subordinate load amounts connected to the two output ports of the i-th stage unit switch, and an input signal is output to the output port with less load. In addition, the load difference information under the i-th stage is constantly fed back to the unit switch of the (i-1) th stage.

[Action]

In the present invention, the Benes network is divided into a distribution network in the first half and a routing network in the second half.
The load connected to two output ports is compared, and the input packet is distributed to the minimum load. Furthermore, the load of the unit switch in the middle of the Benes network is monitored, and the load information is controlled to be returned to the input unit switch by the return signal line.
Therefore, even if a biased input packet is input to the distributed network, it is equalized on the unit switch in the middle of the Benes network, and the throughput can be increased.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows the configuration of the self-routing Benes network which is the object of the present invention. This shows an example of an 8-input 8-output Benes network. The principle of the present invention will be described below with reference to FIG.

The unit switch on the input side is the 0th stage, the unit switch on the output side is the 4th stage unit switch, and it is a multistage switching circuit composed of the distribution network of the first half and the routing network of the latter half. The Benes network is constructed by using the unit switches of the stages as connection switches.

Since the routing network in such a Benes network is a basic connection network, a packet can be self-routed by using a binary-coded terminal number of an intended output terminal. However, if there is a biased input packet, a collision occurs inside the routing network, so it is necessary to distribute the input packets evenly in the distributed network. Therefore, in the present invention, the load (corresponding to the input packet) of the unit switch in the middle of the Benes network (hereinafter referred to as the connection switch) is monitored so that the input packets are evenly distributed in the distributed network, and the load information is monitored. Through the return signal line to return to the input unit switch, the throughput is improved. Hereinafter, the characteristic distributed network of the present invention will be described in detail.

FIG. 1 is a block diagram of a distributed network showing an embodiment of the present invention. This shows an example of a distributed network of 16 input 16 output Benes networks.

The unit switches (connection switches) of the third stage are controlled to have equal loads so that the input packets are evenly distributed in the distribution network. First, the loads of the third-stage unit switches (connection switches) are Q ₃₀ , Q ₃₁ , ..., Q ₃₇ . Control is Q
Make sure that ₃₀ = Q ₃₁ = ... == Q ₃₇ . In setting the route of a packet newly input to the unit switch of the 0th stage, (1) the loads of the two output terminals of the unit switch of the 0th stage are compared. In this case, the load Q ₀₀ connected to the output port 1 is Q ₀₀ = Q ₃₀ + Q ₃₁ + Q ₃₂ + Q _{33 The} load Q ₀₁ connected to the output port 2 is Q ₀₁ = Q ₃₄ + Q ₃₅ + Q ₃₆ + Q ₃₇ .

If Q ₀₀ = Q ₀₁ , they are randomly dispersed.

Q _00> Q ₀₁ if output to the output port 2.

Therefore, each unit switch constantly updates the load information currently held by the subordinate connection unit switch.

(2) When the packet is sent to the routing network, the connection switch in the middle of the Benes network feeds back −1 as the load difference information of the connection switch to the second-stage unit switch.

(3) When the i-th unit switch (1 ≦ i ≦ log ₂ N−1) receives a packet, at the same time, the i-th group is connected to the (i−1) th unit switch that is not the input port. The load difference information is fed back. When the unit switch outputs the packet, at the same time, the unit switch notifies the subordinate unit switch that the load of the group subordinate to the unit switch has increased by one. Packet and load information transfer
This is performed after receiving the strobe signal from the unit switch to be transferred.

(4) Each unit switch has a buffer (queuing) for each input terminal and does not perform priority processing.

FIG. 3 is a diagram showing a detailed configuration example of the minimum value load balancing unit switch circuit in FIG. Here, the unit switch will be described in the case of the i-th stage (1 ≦ i ≦ log ₂ N−1).

In FIG. 3, 1 is a main signal input, 2 is a main signal input, 3
Is a main signal output, 4 is a main signal output, 5 is a main signal input storage buffer, 6 is a main signal input storage buffer, 7 is an output circuit,
8 is an output circuit, 9 is a switch, 10 is an output control circuit, 11 is a comparator, 12 is i-stage group load difference information output to the (i-1) -stage unit switch from which the main signal input 1 is output,
13 is the i-stage group load difference information output to the (i-1) -stage unit switch to which the main signal input 2 is output, and 14 is output from the (i + 1) -stage unit switch to which the main signal output 3 is input. (I + 1) -stage group load difference information, 15 is (i + 1) -stage group load difference information input from the (i + 1) -stage unit switch to which the main signal output 4 is input, and 16 is main signal input 1 output New load difference information from the (i-1) th stage unit switch, 17 is the main signal input 2 is output, 17 is new load difference information from the (i-1) th stage unit switch, 18 is the main signal output 3 The new load difference information input to the unit switch of the (i + 1) th stage is input, 19 is the new load difference information input to the unit switch of the (i + 1) stage to which the main signal output 4 is input, and 20 is the main signal output 3 Is input (i + 1) stage single Output from the position switch (i
+1) stage group load information accumulation buffer, 21 is an (i + 1) stage group load information accumulation buffer output from the (i + 1) stage unit switch to which the main signal output 4 is input, 22
Is an i-stage group load information storage buffer, 23 is an adder,
24 and 25 are latch circuits.

The unit switch includes a main signal system circuit and a load information transfer system circuit. The main signal system has an input queue on each of the two input sides and compares the load information of the (i + 1) th stage to determine the output destination. The load information transfer system circuit includes a circuit system for comparing the load information of the (i + 1) th stage and a circuit system for constantly updating the load information of its own i stage. When new load difference information is input at an arbitrary clock, it is added to its own load information. Further, when the input packet is output to the (i + 1) th stage unit switch, the new load difference information is transferred to the transfer destination unit switch.

First, the main signal system will be specifically described. Main signal input 1,
When the main signal input 2 is input to the unit switch, it is stored in the main signal input storage buffer 5 and the main signal input storage buffer 6, respectively. There are two types of these main signal inputs (i +
1) Stage group load information storage buffers 20 and 21 are connected to comparator 11
In comparison, the output control circuit 10 controls the main signal to output the main signal to the one with the smaller load, and the main signal is switched by the switch 9, and then output to the output circuit 7 or 8.

Next, the load information transfer system will be described. Main signal input 1
When the new load difference information 16 from the unit switch of the (i-1) th stage is output, the latch circuit 24 first latches it, the adder 23 adds it, and the i stage group load information storage buffer 22. Will be updated. Next, this information is output as i-stage group load difference information 13 output to the (i-1) -stage unit switch to which the main signal input 2 is output. Further, regardless of whether the new load difference information is input from 16 or 17, the new load difference information 18 and the main signal output 4 input to the (i + 1) -stage unit switch to which the main signal output 3 is input are input. Is output to both as new load difference information 19 input to the unit switch of the (i + 1) th stage.
Further, the (i + 1) -stage unit load difference information 14 output from the (i + 1) -stage unit switch to which the main signal output 3 is input, and the (i + 1) -stage unit switch to which the main signal output 4 is input are input. The group load information of the i-th stage is updated by the (i + 1) -th stage group load difference information 15.

〔The invention's effect〕

As described above, according to the present invention, in a network that handles multimedia in a unified manner, it is possible to realize an excellent improvement in throughput in terms of the average delay time characteristic and the like as compared with a conventional Banyan network or a random distributed Benes network. it can.

[Brief description of drawings]

FIG. 1 is a block diagram of a distributed network of Benes networks showing an embodiment of the present invention, and FIG. 2 is a self-routing
FIG. 3 is a detailed configuration diagram of the Benes network, and FIG. 3 is a detailed configuration diagram of the minimum value load balancing unit switch in the embodiment of the present invention. 1,2: Main signal input, 3,4: Main signal output, 5,6: Main signal input accumulation buffer, 7,8: Output circuit, 9: Switch, 10: Output control circuit, 11: Comparator, 12, 13: i-stage group load difference information, 14,1
5: (i + 1) -stage group load difference information, 16,17,18,19: new load difference information, 20,21: (i + 1) -stage group load information accumulation buffer, 22: i-stage group load information accumulation buffer, 23 : Adder, 24, 25: Latch circuit.

Claims (1)

(57) [Claims] 1. In an N-input N-output (N: natural number) Benes network composed of (2log ₂ N-1) -stage ₂ -input 2-output unit switches, the input-side unit switch is the 0th stage and the output-side unit switch. Unit switch of the second (2log ₂ N-1) stage, and this Benes network is a multi-stage switching circuit composed of the distribution network of the first half and the routing network of the second half, the unit switch in the middle is the connection switch, In the routing network, the input signal is self-routed by the packet header with the output terminal number expressed in binary, and in the distributed network, the route of the packet newly input to the unit switch of the 0th stage is set by the unit switch of the 0th stage. Compare the loads on the two output ports, and if they are the same, distribute them randomly.
When there is a large or small load, output to a port with a small load,
In addition, the unit switch of the i-th stage (1 ≦ i ≦ log ₂ N−1) holds the load information accumulated in the subordinate connection switch in the distribution network, and the two outputs of the unit switch of the i-th stage. The subordinate loads connected to the ports are compared with each other, the input signal is output to the output port having a small load, and the (i-
1) A high-speed switching circuit characterized by constantly feeding back the load difference information under the i-th stage to the unit switch of the stage.