JPS6419817A - Digital filter - Google Patents

Digital filter

Info

Publication number
JPS6419817A
JPS6419817A JP17476887A JP17476887A JPS6419817A JP S6419817 A JPS6419817 A JP S6419817A JP 17476887 A JP17476887 A JP 17476887A JP 17476887 A JP17476887 A JP 17476887A JP S6419817 A JPS6419817 A JP S6419817A
Authority
JP
Japan
Prior art keywords
multiplier
inputted
adder
digital
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17476887A
Other languages
Japanese (ja)
Inventor
Koki Kuroda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP17476887A priority Critical patent/JPS6419817A/en
Publication of JPS6419817A publication Critical patent/JPS6419817A/en
Pending legal-status Critical Current

Links

Landscapes

  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To obtain a digital filter having a prescribed direct current gain by matching a circuit network having a digital adder, multiplier and an unit delay element and a simple digital multiplier to the respective factors of a digital transfer function H(z). CONSTITUTION:The simple multiplier 1 corresponding to a coefficient C1-n and digital signal data is inputted for every prescribed sampling cycle. The circuit network (z) is constituted of the adder 21, a substracter 22, the multipliers 23, 24 and the unit delay element 25 and to the adder 21, the output of the multipliers 1, 23 is inputted, to the substracter 22, the output of the adder 21 and the multiplier 24 is inputted, to the multipliers 23, 24, the output of the unit delay circuit 25 is inputted and to this unit delay circuit 25, the output of the adder 21 is inputted. The multiplier 23 corresponds to a coefficient C2-n and the multiplier 24 corresponds to a coefficient C3-n. The direct current gain is constantly a prescribed value and a signal level is not fluctuated.
JP17476887A 1987-07-15 1987-07-15 Digital filter Pending JPS6419817A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17476887A JPS6419817A (en) 1987-07-15 1987-07-15 Digital filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17476887A JPS6419817A (en) 1987-07-15 1987-07-15 Digital filter

Publications (1)

Publication Number Publication Date
JPS6419817A true JPS6419817A (en) 1989-01-23

Family

ID=15984332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17476887A Pending JPS6419817A (en) 1987-07-15 1987-07-15 Digital filter

Country Status (1)

Country Link
JP (1) JPS6419817A (en)

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