JPS6418347U - - Google Patents
Info
- Publication number
- JPS6418347U JPS6418347U JP11303287U JP11303287U JPS6418347U JP S6418347 U JPS6418347 U JP S6418347U JP 11303287 U JP11303287 U JP 11303287U JP 11303287 U JP11303287 U JP 11303287U JP S6418347 U JPS6418347 U JP S6418347U
- Authority
- JP
- Japan
- Prior art keywords
- latch
- signal
- bus
- circuit
- cycle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11303287U JPS6418347U (enExample) | 1987-07-23 | 1987-07-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11303287U JPS6418347U (enExample) | 1987-07-23 | 1987-07-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6418347U true JPS6418347U (enExample) | 1989-01-30 |
Family
ID=31352512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11303287U Pending JPS6418347U (enExample) | 1987-07-23 | 1987-07-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6418347U (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02287839A (ja) * | 1989-04-28 | 1990-11-27 | Nec Corp | インサーキット・エミュレータ |
-
1987
- 1987-07-23 JP JP11303287U patent/JPS6418347U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02287839A (ja) * | 1989-04-28 | 1990-11-27 | Nec Corp | インサーキット・エミュレータ |
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