JPS641777Y2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a demodulation circuit that can accurately reproduce an original signal and suppress the generation of unnecessary signals.

BACKGROUND OF THE INVENTION Recent advances in semiconductor integrated circuit technology have been remarkable, and various circuits have been made into semiconductor integrated circuits. Demodulation circuits used in television receivers, radio receivers, or other communication equipment are also examples of this. When implementing such a demodulation circuit into a semiconductor integrated circuit, a particular problem is the generation of unnecessary signals. A demodulation circuit always performs a signal conversion operation, and at this time, spurious signals such as harmonics are generated, significantly deteriorating the characteristics of equipment that incorporates this demodulation circuit, and in some cases, causing interference with other communications. This may cause inconvenience due to interference with equipment.

By the way, when the demodulation circuit is composed of individual components, the above-mentioned disadvantage can be relatively easily eliminated by shielding only the demodulation circuit portion. However, when a demodulation circuit is integrated into a semiconductor, it is common that not only the demodulation circuit part but also the circuit parts before and after it are integrated into a single semiconductor substrate, which may cause the generation of unnecessary signals. It is extremely difficult to shield only a portion. Therefore, unnecessary signals are transmitted within a single semiconductor substrate, and the characteristics of the resulting semiconductor integrated circuit are deteriorated.

In view of these problems, multiplicative demodulation circuits are currently widely used as low-level demodulation circuits that can process about one-tenth or less of a signal compared to conventional demodulation circuits. This multiplier demodulation circuit is called a synchronous demodulation circuit or pseudo-synchronous demodulation circuit when used in a television receiver, and is called a quadrature detection circuit when used for demodulating an FM signal. It is called a circuit.

FIG. 1 is a block diagram showing the configuration of the multiplier type demodulation circuit described above. In the figure, 1 is a terminal to which an input signal is applied, 2 is a circuit section that generates a signal corresponding to the carrier wave of the input signal, and 3 is a circuit section that generates a signal corresponding to the carrier wave of the input signal. A multiplication circuit section generates a demodulated signal by multiplying the input signal by a signal corresponding to a carrier wave generated by the signal generation circuit section 2, 4 is a low-pass filter, and 5 is an output terminal for the demodulated signal.

In the demodulation circuit with the above configuration, the input signal and the signal equivalent to the carrier wave are applied to the multiplier circuit section 3 as described above, but if there is a phase difference between the two signals, the demodulation circuit It is already well known that the characteristics deteriorate. For example, if the level of the demodulated signal generated at the output terminal 5 is "1" when there is no phase difference, it becomes "0" when the phase difference becomes 90 degrees.

Problems to be Solved by the Invention Incidentally, the signal transmission time of the signal generation circuit section 2 corresponding to a carrier wave, which is a component of the multiplier type demodulation circuit shown in FIG. 1, is finite, and a phase delay occurs when a signal is generated. Therefore, a phase difference occurs between the input signal and the demodulated signal, which deteriorates the characteristics of the demodulated signal.

Generally, the original signal (modulated signal) is a composite of signals with different amplitudes and frequencies, so a signal that is a complex combination of beat components of these signals is output to the output terminal 5 as a demodulated signal. Occur. When such a demodulation circuit is used as a video detection circuit for a television receiver, a beat signal (920KHz) consisting of a 4.5MHz audio signal and a 3.58MHz color subcarrier signal is generated, resulting in a significant deterioration in image quality. Furthermore, linearity also deteriorates, resulting in deterioration of differential gain and differential phase.

The occurrence of such inconvenience is particularly noticeable in a pseudo-synchronous demodulation circuit in which the signal generation circuit section 2 includes an amplitude-limiting amplifier and a tank circuit, and is configured to pass the input signal as it is through these circuits to generate a carrier wave. do. That is, a phase delay occurs when the input signal passes through the above-mentioned amplitude limiting amplifier, resulting in a phase difference between the input signal and the input signal.

Means for Solving the Problems The present invention provides a demodulation circuit that can eliminate the above-mentioned disadvantages that are noticeable in conventional demodulation circuits, especially pseudo demodulation circuits. , a circuit section that mainly includes a differential amplifier to which a modulated signal inputted to an input terminal is applied in a differential format, and that generates a carrier wave signal of the modulated signal; and the carrier wave generated by the circuit section. In the demodulation circuit, the demodulation circuit includes a multiplication circuit section which receives a signal and the modulated signal and multiplies them to generate a demodulated signal. A phase compensation circuit section consisting of a differential amplifier constituted by two transistors having a feedback resistor is arranged to match the phase of the modulated signal with the phase of the carrier wave signal.

Operation In the demodulation circuit of the present invention, phase compensation of the input signal can be performed by selecting the value of the collector load resistance.

Embodiments Hereinafter, a demodulation circuit of the present invention will be described along with embodiments with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of the demodulation circuit of the present invention. The difference from the conventional demodulation circuit shown in FIG. The configuration is such that an input signal applied to the input terminal 1 is phase-corrected by the phase compensation circuit section 6 and then applied to the multiplication circuit section 3.

By the way, this phase compensation circuit section 6 has a phase delay effect of imparting to the input signal the same amount of phase delay as the phase delay generated in the signal generation circuit section 2, and the input signal is By applying this to the multiplier circuit section 3, the phase of the input signal and the signal corresponding to the carrier wave applied from the signal generation circuit section 2 to the multiplier circuit section 3 match, and deterioration of the characteristics of the demodulated signal is prevented. Ru.

FIG. 3 is a diagram showing a specific configuration of the demodulation circuit according to the present invention whose basic configuration is shown in FIG. 2. In the figure, 7 and 8 are terminals to which input signals are applied, 9 and 10 are emitter follower transistors,
11 and 12 are transistors forming a differential amplifier for obtaining a carrier signal, 13 and 14 are coils and capacitors forming a selection circuit, 15 and 16 are resistors for DC bias supply, and 17 and 18 are for amplitude limiting. diodes, 19 and 20 are emitter follower transistors, 21 to 25 are resistors for supplying emitter current, 26 and 27 are transistors forming a differential amplifier for converting input signal voltage into current,
28, 29 are emitter resistors of transistors 26 and 27; 30, 31 and 32, 33 are transistors for forming a differential amplifier forming a multiplier circuit;
4 and 35 are transistors for configuring a differential amplifier forming a phase compensation circuit section; 36 to 39 are emitter follower transistors configuring a buffer amplifier for perfecting the effect of the differential amplifier for phase compensation; 4
0 and 41 are emitter feedback resistances of transistors 34 and 35, 42 and 43 are collector load resistances,
44 is a power supply transistor for the differential amplifier for phase compensation, 45 and 46 are resistors for determining the base bias of transistor 44, and 47 to 50 are transistors 36
~39 emitter current supply resistors, 51, 52,
53, 54, 55, and 56 are transistors 1
1, 12, transistors 26, 27 and transistors 34, 35 for current source transistors and resistors, 57 and 5
8 is a diode and a resistor for supplying base bias of the current source transistor, 59 and 60 are output load resistances, 61 and 62 are output terminals, and 6
3 is a power supply terminal for the entire demodulation circuit.

In the demodulation circuit of the present invention configured with the above circuit elements, when an input signal is applied to the input terminals 7 and 8, this input signal passes through the emitter follower transistors 9 and 10 to the transistors 11 and 12. is input to a differential amplifier composed of . In this way, the carrier wave signal applied to the multiplication circuit section has a time difference Δt corresponding to the signal transmission time of the circuit with respect to the input signal. Therefore, if transistor 2 becomes the input terminal of the multiplication circuit section,
When the input signal is directly applied to the base of 6 and 27 and the operating frequency of the circuit is fo, the phase difference Δ between the carrier signal and the input signal is expressed as Δ=2πfoΔt, and the phase difference Δ proportional to the operating frequency is Occur.

By the way, in the present invention, as shown in the figure, the input signal is not directly applied to the multiplier circuit section as described above, but is applied to the emitter follower transistors 36, 3.
The voltage is applied to the bases of the transistors 34 and 35 that constitute the differential amplifier for phase compensation through the transistor 7, and after the phase is compensated here, the transistor becomes the input terminal of the multiplier circuit section via the emitter follower transistors 38 and 39. It is applied to the bases of 26 and 27.

By the way, the phase compensation effect of the phase compensation differential amplifier increases or decreases in accordance with the increase or decrease in the values of the collector load resistances 42 and 43 of the transistors 34 and 35. Therefore, if the phase of the input signal is compensated by selecting the resistance values of the collector load resistors 42 and 43 described above, it becomes possible to match the phase of the input signal applied to the multiplication circuit section and the carrier wave signal. This eliminates the problem of deterioration of the characteristics of the demodulated output caused by the presence of a phase difference between the signals.
1 and 62, a demodulated output without characteristic deterioration can be generated.

When designing the illustrated demodulation circuit, the complexity of the circuit design can be reduced if the ratios of the resistors 40 and 42 and 41 and 43 are set so that the gain of the phase compensation differential amplifier is 1. can.

Effects of the invention As explained above, the demodulation circuit of the invention uses a phase compensation circuit to match the phase of the input signal applied to the multiplication circuit and the carrier signal, thereby eliminating characteristic deterioration of the demodulated output. It is of great practical value.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional multiplicative demodulation circuit, FIG. 2 is a block diagram showing the configuration of the multiplicative demodulation circuit of the present invention, and FIG. 3 is a specific example of the multiplication demodulation circuit shown in FIG. FIG. 2 is a circuit diagram showing a typical configuration. 1, 7, 8...Input signal application terminal, 2...Circuit section that generates a signal corresponding to a carrier wave, 3...Multiplication circuit section, 4...Low pass filter, 5, 61, 6
2...Output terminal, 6...Phase compensation circuit section, 9,1
0, 19, 20, 36-39... Emitter follower transistor, 11, 12... Transistor for differential amplifier configuration for obtaining a carrier signal, 13
... Coil for forming selection circuit, 14 ... Capacitor for forming selection circuit, 15, 16 ... Resistor for DC bias supply, 17, 18 ... Diode for amplitude limiting, 21-25, 47-50 ... Emitter current supply Resistors 26, 27...Transistors for configuring a differential amplifier that converts input signal voltage into current, 2
8, 29... Emitter resistor, 30-33... Transistor for differential amplifier configuration forming the multiplier circuit section, 34, 35... Transistor for differential amplifier configuration forming the phase compensation circuit section, 40, 41 ……
Emitter feedback resistor, 42, 43... Collector load resistance for determining phase compensation effect, 44... Transistor for power supply, 45, 46... Resistor for determining base bias, 51-53... Transistor for current source, 5
4 to 56... Emitter resistance, 57... Base bias supply diode, 58... Base bias supply resistance, 59, 60... Output load resistance, 63
...Power terminal.

Claims (1)

[Scope of utility model registration request] a circuit section that mainly includes a differential amplifier to which a modulated signal inputted to an input terminal is applied in a differential format, and generates a carrier wave signal of the modulated signal;
A multiplication circuit section receives a carrier wave signal generated in the circuit section and the modulated signal and multiplies them to generate a demodulated signal, and a collector circuit section is provided between the input terminal and the multiplication circuit section. A phase compensation circuit section having a symmetrical amplifier configuration that matches the phase of the modulated signal with the phase of the carrier signal, which is composed of a differential amplifier configured with two transistors having a load resistor and an emitter feedback resistor, is disposed. demodulation circuit.