JPS6417289A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS6417289A
JPS6417289A JP62171176A JP17117687A JPS6417289A JP S6417289 A JPS6417289 A JP S6417289A JP 62171176 A JP62171176 A JP 62171176A JP 17117687 A JP17117687 A JP 17117687A JP S6417289 A JPS6417289 A JP S6417289A
Authority
JP
Japan
Prior art keywords
access
time
signal
variation
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62171176A
Other languages
Japanese (ja)
Inventor
Takashi Kumagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62171176A priority Critical patent/JPS6417289A/en
Publication of JPS6417289A publication Critical patent/JPS6417289A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a chip select access from being delayed from an address access, by obtaining an address transition detector signal, based on a control pulse signal at the time of the chip select access. CONSTITUTION:The titled device is provided with an inhibiting circuit 7 for inhibiting an output of a address transition detector ATD circuit 3 for a prescribed time at the time of variation of a chip select CS input signal, and a CS access control circuit 6 for sending out a control pulse signal consisting of a one-shot pulse at the time of variation of the CS input signal, so that an ATD signal can be obtained, based on the control pulse signal at the time of CS access. In such a way, the ATD signal of the same timing as that which is obtained at the time of variation of an address input signal is obtained by the CS access control circuit at the time of variation of the CS input signal, therefore, it can be prevented that the CS access is delayed against an address access.
JP62171176A 1987-07-10 1987-07-10 Semiconductor storage device Pending JPS6417289A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62171176A JPS6417289A (en) 1987-07-10 1987-07-10 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62171176A JPS6417289A (en) 1987-07-10 1987-07-10 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS6417289A true JPS6417289A (en) 1989-01-20

Family

ID=15918408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62171176A Pending JPS6417289A (en) 1987-07-10 1987-07-10 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS6417289A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100402388B1 (en) * 2001-09-24 2003-10-17 삼성전자주식회사 Semiconductor memory device having reduced chip select output time

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100402388B1 (en) * 2001-09-24 2003-10-17 삼성전자주식회사 Semiconductor memory device having reduced chip select output time

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