JPS6416077A - Noise reduction circuit - Google Patents

Noise reduction circuit

Info

Publication number
JPS6416077A
JPS6416077A JP62171479A JP17147987A JPS6416077A JP S6416077 A JPS6416077 A JP S6416077A JP 62171479 A JP62171479 A JP 62171479A JP 17147987 A JP17147987 A JP 17147987A JP S6416077 A JPS6416077 A JP S6416077A
Authority
JP
Japan
Prior art keywords
circuit
level
limiter
signal
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62171479A
Other languages
Japanese (ja)
Inventor
Masami Itoga
Yoshiki Mizutani
Koichi Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62171479A priority Critical patent/JPS6416077A/en
Publication of JPS6416077A publication Critical patent/JPS6416077A/en
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Abstract

PURPOSE:To obtain a desired S/N at all times and to suppress afterimage efficiently by detecting a noise level during the vertical blanking period of a video signal and changing the setting of a limiter level corresponding to the detection level. CONSTITUTION:A limiter level setting circuit 12 sends a signal changing the setting of the limiter level of a limiter circuit 5 in response to an output signal of a noise level detection circuit 11. The circuit 12 sends a signal to increase the limiter level of the limiter circuit 5 when it discriminates that the noise level mixed in the video signal is large in the noise level detection circuit 11 and when it discriminates small mixed in the video signal in the circuit 11, the signal is sent to decrease the limiter level of the circuit 5. Thus, even with various video signals having different S/N applied to the input terminal 1, the noise signal is suppressed with high performance at all times and the after image is suppressed effectively.
JP62171479A 1987-07-09 1987-07-09 Noise reduction circuit Pending JPS6416077A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62171479A JPS6416077A (en) 1987-07-09 1987-07-09 Noise reduction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62171479A JPS6416077A (en) 1987-07-09 1987-07-09 Noise reduction circuit

Publications (1)

Publication Number Publication Date
JPS6416077A true JPS6416077A (en) 1989-01-19

Family

ID=15923868

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62171479A Pending JPS6416077A (en) 1987-07-09 1987-07-09 Noise reduction circuit

Country Status (1)

Country Link
JP (1) JPS6416077A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4926261A (en) * 1988-02-10 1990-05-15 Sony Corporation Video noise reduction circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4926261A (en) * 1988-02-10 1990-05-15 Sony Corporation Video noise reduction circuit

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