JPS64141U - - Google Patents
Info
- Publication number
- JPS64141U JPS64141U JP9634087U JP9634087U JPS64141U JP S64141 U JPS64141 U JP S64141U JP 9634087 U JP9634087 U JP 9634087U JP 9634087 U JP9634087 U JP 9634087U JP S64141 U JPS64141 U JP S64141U
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- cpu
- emulator
- jamming circuit
- break
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Bus Control (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9634087U JPS64141U (en, 2012) | 1987-06-22 | 1987-06-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9634087U JPS64141U (en, 2012) | 1987-06-22 | 1987-06-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS64141U true JPS64141U (en, 2012) | 1989-01-05 |
Family
ID=30961973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9634087U Pending JPS64141U (en, 2012) | 1987-06-22 | 1987-06-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS64141U (en, 2012) |
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1987
- 1987-06-22 JP JP9634087U patent/JPS64141U/ja active Pending