JPS6413636A - Method and device for generating and detecting parity - Google Patents

Method and device for generating and detecting parity

Info

Publication number
JPS6413636A
JPS6413636A JP62170684A JP17068487A JPS6413636A JP S6413636 A JPS6413636 A JP S6413636A JP 62170684 A JP62170684 A JP 62170684A JP 17068487 A JP17068487 A JP 17068487A JP S6413636 A JPS6413636 A JP S6413636A
Authority
JP
Japan
Prior art keywords
parity
generation
detection
setting
main processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62170684A
Other languages
Japanese (ja)
Inventor
Masaru Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62170684A priority Critical patent/JPS6413636A/en
Publication of JPS6413636A publication Critical patent/JPS6413636A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To connect two devices without remodeling hardware even in case of a difference in parity between two devices by controlling parity setting for generation of parity and that for detection of parity in a channel controller by a main processor. CONSTITUTION:Parity setting for generation of parity to data inputted to a computer of one device, that for detection of parity to data outputted from this computer, that for generation of parity to data outputted to the other device, and that for detection of parity to data inputted from the other device are performed in the channel controller, and a parity control circuit 6 is provided which controls respective parity settings independently of one another by the indication of a main processor 1. Since parity setting for generation of parity and parity setting for detection of parity which are performed in a channel controller 5 are controlled by the main processor 1, data is transmitted between devices different in parity from each other without remodeling hardware.
JP62170684A 1987-07-07 1987-07-07 Method and device for generating and detecting parity Pending JPS6413636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62170684A JPS6413636A (en) 1987-07-07 1987-07-07 Method and device for generating and detecting parity

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62170684A JPS6413636A (en) 1987-07-07 1987-07-07 Method and device for generating and detecting parity

Publications (1)

Publication Number Publication Date
JPS6413636A true JPS6413636A (en) 1989-01-18

Family

ID=15909476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62170684A Pending JPS6413636A (en) 1987-07-07 1987-07-07 Method and device for generating and detecting parity

Country Status (1)

Country Link
JP (1) JPS6413636A (en)

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