JPS6411740U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a timing chart of the signals of the main parts of the block diagram, and Figure 3 is an overall diagram of a conventional image recording device.
FIG. 4 is a plan view of the optical writing device, and FIG. 5 is a block diagram of a conventional buffer control circuit. 31...S-P conversion circuit, 32...Buffer RAM
, 33...address selector, 34...address generation circuit, 35...data selector, 37...timing control unit.

Claims (1)

[Claims for Utility Model Registration] (1) An S-P conversion circuit that converts input data to be printed from serial to parallel, and a time-sharing method for storing and reading data converted into parallel by the S-P conversion circuit. the buffer RAM, an address selector that selectively supplies a write address and a read address to the buffer RAM, and an address generation circuit that generates the write address and read address; A buffer control circuit for a printing device, characterized in that a RAM, an address selector, and an address generation circuit are configured in one system. (2) The utility model registration claim 1 is characterized in that the operations of the S-P conversion circuit, buffer RAM, address selector, and address generation circuit are controlled by signals output from a timing control section. A buffer control circuit for the printing device according to item 1.