JPS6410494A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS6410494A
JPS6410494A JP62167164A JP16716487A JPS6410494A JP S6410494 A JPS6410494 A JP S6410494A JP 62167164 A JP62167164 A JP 62167164A JP 16716487 A JP16716487 A JP 16716487A JP S6410494 A JPS6410494 A JP S6410494A
Authority
JP
Japan
Prior art keywords
bit line
preamplifier
node
sensitivity
charge transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62167164A
Other languages
Japanese (ja)
Inventor
Kiyohiro Furuya
Kazutami Arimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62167164A priority Critical patent/JPS6410494A/en
Publication of JPS6410494A publication Critical patent/JPS6410494A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain high-sensitivity and high-speed amplification by charging/ discharging directly a bit line from a sense amplifier terminal after the initial amplification of the sense operation is applied via a charge transfer preamplifier and a capacitor. CONSTITUTION:When a memory cell 2a storing '1' is selected, the potential of a bit line 1a precharged to 1/2VCC is increased slightly more than that of the bit line 1b and the level of a node N9 rises slightly higher than that of a node N8 via a capacitor C6 of a charge transfer preamplifier PA. Thus, a transistor (TR) Q18 is turned on and a TR Q17 is turned off and the charge of a node N5 is transferred to the bit line 1b. Then a potential difference amplified correspondingly to a potential difference the bit lines 1a and 1b in nodes N10, N11 is fed directly to a terminal of a sense amplifier SA and the storage content is read. This operation is applied to the storage content 0 similarly and the high-sensitivity and high-speed amplification is applied by using the high-sensitivity charge transfer preamplifier.
JP62167164A 1987-07-02 1987-07-02 Semiconductor storage device Pending JPS6410494A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62167164A JPS6410494A (en) 1987-07-02 1987-07-02 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62167164A JPS6410494A (en) 1987-07-02 1987-07-02 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS6410494A true JPS6410494A (en) 1989-01-13

Family

ID=15844602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62167164A Pending JPS6410494A (en) 1987-07-02 1987-07-02 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS6410494A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000149567A (en) * 1998-11-09 2000-05-30 Oki Electric Ind Co Ltd Semiconductor memory device
JP2011093531A (en) * 2007-01-17 2011-05-12 Polaris Industries Inc Windshield assembly for vehicle

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000149567A (en) * 1998-11-09 2000-05-30 Oki Electric Ind Co Ltd Semiconductor memory device
JP2011093531A (en) * 2007-01-17 2011-05-12 Polaris Industries Inc Windshield assembly for vehicle

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