JPS641033U

JPS641033U -

Info

Publication number: JPS641033U
Application number: JP9190387U
Authority: JP
Priority date: 1987-06-17
Filing date: 1987-06-17
Publication date: 1989-01-06

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例の回路図、第２図は
第１図記載の制御回路４７の供給電力停止時の制
御回路図、第３図は第１図記載の制御回路４７の
供給電力開始時の制御回路図、第４図は本考案の
動作説明図、第５図、第６図は本考案のタイムチ
ヤート、第７図は従来例の回路図、第８図は従来
例のタイムチヤートである。７Ａ……電力順変換装置、８……電力逆変換装
置、９Ａ……直流力行母線、９Ｂ……直流回生母
線、１２……高配負荷、１３……電源母線、１４
……電源、１５Ａ，１６Ａ……交流しや断器、１
９，２０……直流リアクトル、２１……直流負極
母線、３３Ａ，３３Ｂ……電車、４７……制御回
路、４８……ゲートブロツク回路、４９……ゲー
トシフト回路、６１……第一工程、６２……第二
工程、６３……第三工程、６４……全き電回停電
、６５……切指令信号、６６……パルス回路出力
信号、６７……ゲートブロツク、６８……ゲート
シフト、６９……ＯＦＦモード、７０……ゲート
付整流素子導通期間、７１……パルス信号復帰、
７２……コンバータ通常モード、７３……インバ
ータ通常モード、７４……ＯＦＦモード、７５…
…遅延回路出力信号、７６……断路器操作期間、
７７……全き電回路停電、７８……再給電、７９
……入指令信号、８０……断路器操作期間、８１
……遅延回路出力信号、８２……ＯＮモード、８
３……ゲート付整流素子導通期間。 FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a control circuit diagram when power supply to the control circuit 47 shown in FIG. 1 is stopped, and FIG. 3 is a circuit diagram of the control circuit 47 shown in FIG. A control circuit diagram at the time of power start, Fig. 4 is an explanatory diagram of the operation of the present invention, Figs. 5 and 6 are time charts of the present invention, Fig. 7 is a circuit diagram of the conventional example, and Fig. 8 is a diagram of the conventional example. It is a time chart. 7A...Power forward conversion device, 8...Power inversion device, 9A...DC power running bus, 9B...DC regeneration bus, 12...High distribution load, 13...Power supply bus, 14
...Power supply, 15A, 16A...AC switch, 1
9, 20... DC reactor, 21... DC negative electrode bus, 33A, 33B... Train, 47... Control circuit, 48... Gate block circuit, 49... Gate shift circuit, 61... First step, 62 ...Second process, 63...Third process, 64...Complete power outage, 65...Cut command signal, 66...Pulse circuit output signal, 67...Gate block, 68...Gate shift, 69 ...OFF mode, 70...Gated rectifier conduction period, 71...Pulse signal recovery,
72...Converter normal mode, 73...Inverter normal mode, 74...OFF mode, 75...
...Delay circuit output signal, 76...Disconnector operation period,
77... Complete power outage, 78... Repowering, 79
...Incoming command signal, 80...Disconnector operation period, 81
...Delay circuit output signal, 82 ...ON mode, 8
3...Gated rectifier element conduction period.

Claims

[Scope of utility model registration request]

A gated power forward conversion device is connected to a DC power running bus, a gated power reverse conversion device is connected to a DC regeneration bus, and for each feeder line, the power is connected in the forward direction from the DC power running bus, and from the DC regeneration bus in the forward direction. In a feeding device for an electric railway substation in which diodes are connected in opposite directions and connected to the feeder line via a disconnect switch, the diodes use a gated rectifying element and connect to the gate circuit of the gated rectifying element for power forward conversion. A feeding device for an electric railway substation, characterized in that a control circuit is provided between a gate circuit of the device, a gate circuit of a power inversion device, and a disconnector operating circuit.