JPS6396952A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce an occupied area and to stabilize the operation of a transistor by a method wherein a capacitor part and a transistor part for a memory cell are formed in the vertical direction on the surface of a substrate and the substrate and a channel region are brought into contact with each other by means of a layer of the same conductivity type. CONSTITUTION:A groove 2 is made on a P-type Si substrate 1. A P<+> layer 3 is formed, by diffusion, at the bottom of this groove; an N-type layer 4 is formed, by diffusion, at the sidewall of the groove. The surface of the layer 4 is covered with an oxide film 5; the inside of the groove 2 is filled with P-type polycrystalline Si 6. A capacitor is made up of the layers 3 and 4 and the polycrystalline Si 6. Then, the upper part of the groove 2 is coated with an oxide film 7. A P-type polycrystalline Si is deposited on this film so that it can be transformed into a P-type single crystal after laser annealing. After that, an N-type source region 9 and an N-type drain region 10 are formed, by diffusion, at this part, and are abutted on the substrate 1 while said single crystal remaining sandwiched by these regions is used as a channel region 8 so that a polycrystalline gate electrode 11 which is buried in an interlayer insulating film 12 can be installed above the channel region. Then, an opening is made on the film 12; an Al wiring part 13 coming into contact with the region 10 is formed while the opening is being buried.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device using MOS transistors, and particularly to a dynamic memory having a cell structure of one transistor and one capacitor.

Conventional technology In conventional semiconductor memory devices, a groove is dug on the substrate surface and the side and bottom surfaces are used as capacitor electrodes, so that the capacitance of the capacitor does not decrease even if the area occupied by the capacitor on the surface of the semiconductor substrate is reduced. In some cases, the transistor and capacitor parts were located side by side on the surface of the semiconductor substrate.

In addition, 5OI (5il) is placed on the capacitor formed in the groove.
A method has also been proposed in which island-shaped MOS transistors formed using MOS transistor technology are formed and used as memory cells, but this differs from ordinary MOS transistors in that the channel part is It is cut off from the semiconductor substrate and the substrate potential cannot be fixed.

Problems to be Solved by the Invention However, with the above configuration, in a memory cell where the substrate potential can be fixed, the transistor part and the capacitor part are located side by side on the semiconductor substrate, so the memory cell is occupied. The area becomes that much larger.

In view of the following points, the present invention is a semiconductor memory device that has a structure that can fix the substrate potential, minimizes the area occupied by memory cells as much as possible, and achieves ultra-high integration of LSI.

Means for Solving the Problems The present invention forms a capacitor in a groove provided on the surface of a semiconductor substrate, covers the upper part of the capacitor and a part of the semiconductor substrate with an insulating film, and further covers the upper part of the capacitor and the semiconductor substrate with a polycrystalline film. The polycrystalline silicon is covered with silicon, and the formed polycrystalline silicon is made into a single crystal by laser annealing to form a MOS transistor. This is a semiconductor memory device that connects two.

Operation According to the above-described structure, the present invention makes it possible to construct a memory cell with a small occupied area and to fix the substrate potential.

Example A more detailed explanation will be given below based on the drawings.

The figure shows a cross-sectional view of a semiconductor memory device according to the present invention. p
In a groove 2 provided in a type silicon substrate 1, 3 is a p+ type bottom surface whose impurity concentration is higher than that of the substrate 1, 4 is a side wall diffused into a fin type, and an n type side wall 4 is covered with an oxide film 6. There is. Groove portion 2 is again filled with p-type polycrystalline silicon e, leaving a small portion above. These n-type side walls 4,
A capacitor is formed by polycrystalline silicon 6 and sidewall oxide film 6. The upper part of the groove part 2 is an n-type side wall 5.
The upper part is left and covered with an oxide film 7. This is p-type polycrystalline silicon formed by depositing p-type polycrystalline silicon on top of the oxide film 7 and then single-crystallizing it by laser annealing, etc. Part of it is diffused to form n-type sources 9 and drains. 10
, a channel region 8 and a polycrystalline silicon gate electrode 11 are provided, thereby forming a MOS transistor. The source region 9 is configured to contact the n-type sidewall 6. Channel region 8 and silicon substrate 1
・Because they are of the same conductivity type (p type) and are in contact with each other, the substrate potential of the channel portion can be taken, ensuring stable operation of the transistor. Furthermore, since the transistor section and capacitor section are configured in a direction perpendicular to the substrate surface,
The area occupied by the memory cell can be made extremely small. 12 is an interlayer oxide film, and 13 is an aluminum wiring.

Effects of the Invention As mentioned above, the capacitor section and the transistor section of the memory cell are configured in a direction perpendicular to the substrate surface, which occupies an extremely small area, and the transistor is stabilized by taking the substrate potential of the channel section. Memory cells can be configured to enable operation. Therefore, the semiconductor memory device according to the present invention is of extremely high industrial value.

[Brief explanation of the drawing]

The figure is a sectional view of a semiconductor memory device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...P-type silicon substrate, 2...Groove portion, 3...P+ type bottom surface, 4...N-type side wall, 5...... Capacitor oxide film, 6... Polycrystalline silicon storage electrode, 7... Separation oxide film, 8
... Channel region, 9 ... Source region, 1o ... Drain region, 11 ... Gate electrode, 12 ... Aluminum wiring.

Claims (1)

[Claims] The groove is filled through a second conductivity type side wall formed on the surface of the groove provided on the surface of the first conductivity type semiconductor substrate and an insulating film covering the second conductivity type side wall. a first conductive conductor, which forms a storage capacitor with polycrystalline silicon, covers a part of the surface of the groove with an insulating film, and is formed across the semiconductor substrate above the insulating film and outside the groove. a drain region of a second conductivity type formed on the semiconductor substrate across the channel portion, and a drain region of a second conductivity type formed on the semiconductor substrate in contact with the sidewall of the second conductivity type of the groove portion. A semiconductor memory device including a transistor having a biconductive type source region.