JPS6395717A - Signal receiving circuit - Google Patents

Signal receiving circuit

Info

Publication number
JPS6395717A
JPS6395717A JP61240522A JP24052286A JPS6395717A JP S6395717 A JPS6395717 A JP S6395717A JP 61240522 A JP61240522 A JP 61240522A JP 24052286 A JP24052286 A JP 24052286A JP S6395717 A JPS6395717 A JP S6395717A
Authority
JP
Japan
Prior art keywords
voltage
signal
threshold voltage
threshold
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61240522A
Other languages
Japanese (ja)
Inventor
Yoshiaki Sutani
須谷 良昭
Yukio Kobayashi
幸夫 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Kansai Communication Systems Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Kansai Communication Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Kansai Communication Systems Ltd filed Critical Fujitsu Ltd
Priority to JP61240522A priority Critical patent/JPS6395717A/en
Publication of JPS6395717A publication Critical patent/JPS6395717A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/08Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H03K5/082Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Dc Digital Transmission (AREA)
  • Interface Circuits In Exchanges (AREA)

Abstract

PURPOSE:To prevent the generation of a digital signal from an irregular bipolar signal due to noise or the like by providing a lower limit on a threshold voltage in generating a digital signal through the comparison between the rectified bipolar signal voltage and the threshold voltage changing in response to the voltage. CONSTITUTION:A regulating voltage of a prescribed level generated by a level setting means 4 is fed to a threshold value generating circuit 3, compared with a threshold voltage changing in proportion to the bipolar signal voltage generated from the circuit 3 and rectified, and either higher voltage is outputted as a threshold voltage. Thus, the threshold voltage is not less than the regulated voltage. Since the regulated voltage is set higher than the output voltage of a rectifier circuit 1 receiving a bipolar signal of a minute level due to crosstalk or the like, even if the bipolar signal of a minute level due to crosstalk of the like is received. the output voltage of the rectifier circuit 1 is below the threshold voltage and a comparator 2 does not generate the digital signal. which compares the output voltage of the rectifier circuit 1 and the threshold voltage.

Description

【発明の詳細な説明】 〔概要〕 信号受信回路において、整流されたバイポーラ信号の電
圧と、その電圧に対応して変化するしきい値電圧とを比
較してディジタル信号を発生する際、しきい値電圧に下
限を設けて、雑音等による不正規のバイポーラ信号から
ディジタル信号が発生するのを防止するようにするもの
である。
[Detailed Description of the Invention] [Summary] In a signal receiving circuit, when generating a digital signal by comparing the voltage of a rectified bipolar signal and a threshold voltage that changes in accordance with the voltage, a threshold value is determined. A lower limit is set on the value voltage to prevent a digital signal from being generated from an irregular bipolar signal due to noise or the like.

〔産業上の利用分野〕[Industrial application field]

本発明は、ディジタル交換機のディジタル加入者回路等
に使用される信号受信回路の改良に関する。
The present invention relates to improvements in signal receiving circuits used in digital subscriber circuits of digital exchanges and the like.

ディジタル電話機等から送られるバイポーラ信号は、デ
ィジタル加入者回路の信号受信回路で受信され、ディジ
タル信号に変換されて交換機側に送られるが、受信信号
が停止した場合、漏話等による微小レベルの信号を正規
の信号と誤ってディジクル信号に変換することがあるた
め、微小レベルの信号では動作しない信号受信回路の提
供が要望される。
Bipolar signals sent from digital telephones, etc. are received by the signal receiving circuit of the digital subscriber circuit, converted to digital signals, and sent to the exchange side. However, if the received signal stops, the signal at a minute level due to crosstalk etc. There is a need to provide a signal receiving circuit that does not operate with very small level signals because the signal may be mistakenly converted into a digital signal.

〔従来の技術〕[Conventional technology]

第3図は従来例の信号受信回路図、第4図は第3図の主
要部の電圧波形説明図である。
FIG. 3 is a signal receiving circuit diagram of a conventional example, and FIG. 4 is a voltage waveform explanatory diagram of the main part of FIG. 3.

ディジタル電話機等から送られるバイポーラ信号はフィ
ルタ等を経由しているため、整流回路1の人力点aでは
第4図(a)の如き電圧波形となって整流回路1に受信
され、整流された出力は点すで第4図(b)の如き電圧
波形となってコンパレータ2に送られる。
Since the bipolar signal sent from a digital telephone etc. passes through a filter etc., at the input point a of the rectifier circuit 1, the voltage waveform as shown in Fig. 4(a) is received by the rectifier circuit 1, and the rectified output is The voltage waveform shown in FIG. 4(b) is now sent to the comparator 2.

整流回路1の出力はピーク値検出回路31にも送られ、
該出力のピーク電圧が検出され、点Cでは第4図(c)
の如き電圧波形が出力される。
The output of the rectifier circuit 1 is also sent to the peak value detection circuit 31,
The peak voltage of the output is detected, and at point C, as shown in Fig. 4(c)
A voltage waveform like this is output.

増幅器32は、出力が上記ピーク電圧の%の電圧になる
ようにピーク値検出回路31の出力を増幅し、ダイオー
ドDを経由してコンデンサCをチャージする。従って、
点dの電圧は第4図(d)に示す如く上記ピーク電圧の
2の電圧となり、バイポーラ信号電圧に対応して変化す
るしきい値電圧が発生される。
The amplifier 32 amplifies the output of the peak value detection circuit 31 so that the output becomes a voltage % of the peak voltage, and charges the capacitor C via the diode D. Therefore,
The voltage at point d becomes two times the peak voltage as shown in FIG. 4(d), and a threshold voltage is generated that changes in accordance with the bipolar signal voltage.

コンパレータ2は点すの電圧波形と点dのしきい値電圧
を比較して受信信号の符号“0”、“1”を判定し、点
eに第4図(e)の如きディジタル信号を発生する。
Comparator 2 compares the voltage waveform at point d with the threshold voltage at point d, determines whether the received signal is ``0'' or ``1'', and generates a digital signal at point e as shown in Figure 4(e). do.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の信号受信回路にあっては、整流されたバイポーラ
信号の符号“0”、“1″を判定するしきい値電圧が、
受信したバイポーラ信号電圧に応じて変化する。このた
め、正常な受信信号が停止した際に漏話等による微小レ
ベルのバイポーラ信号を受信すると、しきい値電圧もそ
れに対応して小さくなるため、正規な信号とみなしてデ
ィジタル信号を発生し交換機を誤動作させる問題点があ
る。
In the conventional signal receiving circuit, the threshold voltage for determining the sign "0" or "1" of the rectified bipolar signal is
Varies depending on the received bipolar signal voltage. Therefore, if a micro-level bipolar signal due to crosstalk or the like is received when a normal received signal has stopped, the threshold voltage will correspondingly decrease, and the exchange will consider it to be a normal signal and generate a digital signal. There are problems that can cause it to malfunction.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

第1図は本発明の原理ブロック図である。 FIG. 1 is a block diagram of the principle of the present invention.

図において、1はバイポーラ信号を整流する整流回路、
3は整流回路1の出力電圧に応じて変化するしきい値電
圧を発生するしきい値発生回路、2は整流回路1の出力
電圧と前記しきい値電圧とを比較してディジタル信号を
発生するコンパレータである。
In the figure, 1 is a rectifier circuit that rectifies a bipolar signal;
3 is a threshold generation circuit that generates a threshold voltage that changes according to the output voltage of the rectifier circuit 1; 2 is a threshold generator that generates a digital signal by comparing the output voltage of the rectifier circuit 1 and the threshold voltage; It is a comparator.

4は本発明に係わり、一定レベルの規制電圧を発生し、
しきい値発生回路3に該電圧を加えるレベル設定手段で
ある。この手段により問題点が解決される。
4 relates to the present invention and generates a regulated voltage of a certain level,
This is level setting means for applying the voltage to the threshold generation circuit 3. This measure solves the problem.

〔作用〕[Effect]

レベル設定手段4で発生される一定レベルの規制電圧は
、しきい値発生回路3に加えられ、該回路で発生された
整流されたバイポーラ信号電圧に比例して変化するしき
い値電圧と比較され、いづれか高い方がしきい値電圧と
して出力される。
The constant level regulation voltage generated by the level setting means 4 is applied to the threshold generation circuit 3 and compared with a threshold voltage that changes in proportion to the rectified bipolar signal voltage generated by the circuit. , whichever is higher is output as the threshold voltage.

このため、しきい値電圧は規制電圧以下となることはな
い。
Therefore, the threshold voltage never becomes lower than the regulation voltage.

規制電圧は、漏話等による微小レベルのバイポーラ信号
を受信した整流回路1の出力電圧より高く設定されてい
るので、漏話等による微小レベルのバイポーラ信号を受
信しても、整流回路1の出力電圧はしきい値電圧以下で
あり、整流回路1の出力電圧としきい値電圧とを比較し
たコンパレータ2が正常な信号とみなしてディジタル信
号を発生させることはない。
The regulated voltage is set higher than the output voltage of the rectifier circuit 1 that has received a minute level bipolar signal due to crosstalk, etc., so even if a minute level bipolar signal due to crosstalk or the like is received, the output voltage of the rectifier circuit 1 is The voltage is below the threshold voltage, and the comparator 2 that compares the output voltage of the rectifier circuit 1 with the threshold voltage considers it to be a normal signal and does not generate a digital signal.

カクシて、漏話等による微小レベルのパイボーライ3号
でディジタル信号が発生し、交換機が誤動作することが
なくなる。
A digital signal is generated at the very small level of Pai Borai No. 3 due to crosstalk, etc., and the switching equipment will no longer malfunction.

〔実施例〕〔Example〕

以下図示実施例により本発明を具体的に説明する。 The present invention will be specifically explained below with reference to illustrated examples.

第2図は本発明の1実施例の信号受信回路である。企図
を通じ同一符号は同一対象物を示す。
FIG. 2 shows a signal receiving circuit according to one embodiment of the present invention. The same reference numerals refer to the same objects throughout the design.

第2図において、抵抗R1,R2,R3は第1図のレベ
ル設定手段4に対応する。
In FIG. 2, resistors R1, R2, and R3 correspond to the level setting means 4 in FIG.

第2図において、抵抗R1,112により作成された電
圧は抵抗R3を介してコンデンサCをチャージし、一定
レベルの規制電圧を保持させている。
In FIG. 2, the voltage created by resistors R1 and 112 charges a capacitor C via a resistor R3 to maintain a regulated voltage at a constant level.

該規制電圧は、漏話等による微小レベルのバイポーラ信
号を受信した整流回路1の出力電圧より高く設定されて
いる。
The regulated voltage is set higher than the output voltage of the rectifier circuit 1 that has received a minute level bipolar signal due to crosstalk or the like.

微小レベルのバイポーラ信号を受信した場合、整流回路
1の出力電圧から、ピーク値検出回路31及び増幅器3
2により、バイポーラ信号に応じて変化するしきい値電
圧が作成されるが、上記規制電圧より低いので、しきい
値電圧としては規制電圧が用いられる。
When a minute level bipolar signal is received, the output voltage of the rectifier circuit 1 is determined by the peak value detection circuit 31 and amplifier 3.
2, a threshold voltage that changes depending on the bipolar signal is created, but since it is lower than the above-mentioned regulation voltage, the regulation voltage is used as the threshold voltage.

このため、微小レベルのバイポーラ信号を受信してもコ
ンパレータ2の判定は符号“0″となり、誤ったディジ
タル信号を発生することはない。
Therefore, even if a very small level bipolar signal is received, the comparator 2 will make a determination of "0", and no erroneous digital signal will be generated.

正常なバイポーラ信号を受信した場合は、ピーク値検出
回路31及び増幅器32により作成された、バイポーラ
信号電圧に応じて変化するしきい値電圧が規制電圧より
裔いため、該しきい値電圧を用いてコンパレータ2は受
信信号の符号“0”、“1”を判定しディジタル信号を
発生する。
When a normal bipolar signal is received, the threshold voltage created by the peak value detection circuit 31 and amplifier 32, which changes according to the bipolar signal voltage, is descended from the regulation voltage, so the threshold voltage is used to The comparator 2 determines whether the received signal is ``0'' or ``1'' and generates a digital signal.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く本発明にあっては、漏話等の微小レベ
ルのバイポーラ信号を受信しても、信号受信回路が正常
な信号とみなしてディジタル信号を発生させることがな
いので、交換機の誤動作がな(なる効果がある。
As explained above, in the present invention, even if a minute level bipolar signal such as crosstalk is received, the signal receiving circuit considers it to be a normal signal and does not generate a digital signal, thereby preventing malfunction of the exchange. (There is an effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理ブロック図、 第2図は本発明の1実施例の信号受信回路図、第3図は
従来例の信号受信回路図、 第4図は第3図の主要部分の電圧波形説明図である。 図において、 1は整流回路、 2はコンパレータ、 3はしきい値発生回路、 4はレベル設定手段を示す。
Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a signal receiving circuit diagram of an embodiment of the present invention, Fig. 3 is a signal receiving circuit diagram of a conventional example, and Fig. 4 shows the main parts of Fig. 3. It is a voltage waveform explanatory diagram. In the figure, 1 is a rectifier circuit, 2 is a comparator, 3 is a threshold generation circuit, and 4 is a level setting means.

Claims (1)

【特許請求の範囲】 バイポーラ信号を受信して整流する整流回路(1)と、
前記整流回路(1)の出力電圧に応じて変化するしきい
値電圧を発生するしきい値発生回路(3)と、前記整流
回路(1)の出力電圧と前記しきい値発生回路(3)の
しきい値電圧とを比較してディジタル信号を発生するコ
ンパレータ(2)からなる信号受信回路において、 一定レベルの規制電圧を発生し、前記規制電圧を前記し
きい値発生回路(3)に加えるレベル設定手段(4)を
設け、 前記しきい値発生回路(3)の出力するしきい値電圧が
前記規制電圧以下にならないようにしたことを特徴とす
る信号受信回路。
[Claims] A rectifier circuit (1) that receives and rectifies a bipolar signal;
a threshold generation circuit (3) that generates a threshold voltage that changes depending on the output voltage of the rectification circuit (1); and an output voltage of the rectification circuit (1) and the threshold generation circuit (3). In a signal receiving circuit consisting of a comparator (2) that generates a digital signal by comparing the voltage with a threshold voltage of A signal receiving circuit characterized in that a level setting means (4) is provided, and the threshold voltage outputted from the threshold voltage generation circuit (3) is prevented from becoming lower than the regulation voltage.
JP61240522A 1986-10-09 1986-10-09 Signal receiving circuit Pending JPS6395717A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61240522A JPS6395717A (en) 1986-10-09 1986-10-09 Signal receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61240522A JPS6395717A (en) 1986-10-09 1986-10-09 Signal receiving circuit

Publications (1)

Publication Number Publication Date
JPS6395717A true JPS6395717A (en) 1988-04-26

Family

ID=17060778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61240522A Pending JPS6395717A (en) 1986-10-09 1986-10-09 Signal receiving circuit

Country Status (1)

Country Link
JP (1) JPS6395717A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0352349A (en) * 1989-07-19 1991-03-06 Fujitsu Denso Ltd Burst signal control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0352349A (en) * 1989-07-19 1991-03-06 Fujitsu Denso Ltd Burst signal control system

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