JPS6393646U - - Google Patents

Info

Publication number
JPS6393646U
JPS6393646U JP1986189362U JP18936286U JPS6393646U JP S6393646 U JPS6393646 U JP S6393646U JP 1986189362 U JP1986189362 U JP 1986189362U JP 18936286 U JP18936286 U JP 18936286U JP S6393646 U JPS6393646 U JP S6393646U
Authority
JP
Japan
Prior art keywords
semiconductor pellet
semiconductor
molded
covered
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986189362U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986189362U priority Critical patent/JPS6393646U/ja
Publication of JPS6393646U publication Critical patent/JPS6393646U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP1986189362U 1986-12-08 1986-12-08 Pending JPS6393646U (Direct)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986189362U JPS6393646U (Direct) 1986-12-08 1986-12-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986189362U JPS6393646U (Direct) 1986-12-08 1986-12-08

Publications (1)

Publication Number Publication Date
JPS6393646U true JPS6393646U (Direct) 1988-06-17

Family

ID=31141593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986189362U Pending JPS6393646U (Direct) 1986-12-08 1986-12-08

Country Status (1)

Country Link
JP (1) JPS6393646U (Direct)

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