JPS6393638U - - Google Patents
Info
- Publication number
- JPS6393638U JPS6393638U JP1986189467U JP18946786U JPS6393638U JP S6393638 U JPS6393638 U JP S6393638U JP 1986189467 U JP1986189467 U JP 1986189467U JP 18946786 U JP18946786 U JP 18946786U JP S6393638 U JPS6393638 U JP S6393638U
- Authority
- JP
- Japan
- Prior art keywords
- wire bonding
- substrate
- semiconductor pellet
- wire
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000008188 pellet Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第1図は本考案の一実施例としての半導体装置
の平面図、第2図は従来例の半導体装置の平面図
である。 1…基板、2…半導体ペレツト、3a,3b…
ワイヤボンデイングパツド、4a,4b…リード
端子、5…ワイヤ。
の平面図、第2図は従来例の半導体装置の平面図
である。 1…基板、2…半導体ペレツト、3a,3b…
ワイヤボンデイングパツド、4a,4b…リード
端子、5…ワイヤ。
Claims (1)
- 【実用新案登録請求の範囲】 基板上に半導体ペレツトが取付けられ、該半導
体ペレツトの表面には大きさの異なるワイヤボン
デイングパツドが2つ以上あつて、各ワイヤボン
デイングパツドとリード端子とがワイヤボンデイ
ングによつて接続されてなる半導体装置において
、 前記複数のワイヤボンデイングパツドのうち面
積の狭小のものが、これに接続されるリード端子
から離れた側にある状態で、前記半導体ペレツト
が基板上に取付けられていることを特徴とする半
導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986189467U JPS6393638U (ja) | 1986-12-09 | 1986-12-09 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986189467U JPS6393638U (ja) | 1986-12-09 | 1986-12-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6393638U true JPS6393638U (ja) | 1988-06-17 |
Family
ID=31141796
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986189467U Pending JPS6393638U (ja) | 1986-12-09 | 1986-12-09 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6393638U (ja) |
-
1986
- 1986-12-09 JP JP1986189467U patent/JPS6393638U/ja active Pending