JPS639154A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS639154A JPS639154A JP15293886A JP15293886A JPS639154A JP S639154 A JPS639154 A JP S639154A JP 15293886 A JP15293886 A JP 15293886A JP 15293886 A JP15293886 A JP 15293886A JP S639154 A JPS639154 A JP S639154A
- Authority
- JP
- Japan
- Prior art keywords
- layer member
- upper layer
- electrode
- source electrode
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 238000000034 method Methods 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 229910021332 silicide Inorganic materials 0.000 abstract description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 18
- 238000005530 etching Methods 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 14
- 238000005468 ion implantation Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
- H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
Abstract
Description
【発明の詳細な説明】
（概要〕
本発明は例えばＭＯＳ Ｆ Ｅ Ｔ等の半導体装置の製
造方法において、
ドレイン及びソースをしＤＤ（ライトリ・ドープド・ド
レイン）化する際工程が増加する問題点を解決するため
、
上層部材を下履部材に比して大きくなるようにしてポリ
サイドゲート電極を形成し、上層部材を遮蔽としてイオ
ン注入を行なってドレイン電極及びソース電極を形成す
ることにより、
少ない工程で、短時間で製造し得るようにしたものであ
る。[Detailed Description of the Invention] (Summary) The present invention solves the problem of increasing the number of steps when converting drains and sources into DD (Lightly Doped Drain) in the manufacturing method of semiconductor devices such as MOSFETs. In order to solve this problem, the polycide gate electrode is formed by making the upper layer member larger than the insole member, and the drain electrode and source electrode are formed by ion implantation using the upper layer member as a shield, thereby reducing the number of steps. This allows it to be manufactured in a short period of time.
本発明は半導体装置、特に、ＭＯＳＦＥＴのドレイン及
びソースをＬＤＤ化する製造方法に関する。ＭＯＳＦＥ
Ｔではドレイン及びソースのゲートエツジに対向した部
分のイオン注入のドープ騎を他の部分に比して少ない構
成にする（ＬＤＤ化。The present invention relates to a semiconductor device, and particularly to a manufacturing method for converting the drain and source of a MOSFET into an LDD. MOSFE
In T, the portions of the drain and source facing the gate edge are doped with less ion implantation than other portions (LDD).
レトロ化）ことにより、特に、ドレインとゲートとの間
の部分の抵抗を高くしてこの部分に電界の集中するのを
和らげ、トレイン及びゲート間の絶縁破壊を防止し、ゲ
ート接合容量を減少させている。このような構造のＭＯ
ＳＦＥＴを製造するに際し、少ない工程で短時間で’！
Ｉ Ｓすることが必要である。In particular, by increasing the resistance of the region between the drain and gate, it alleviates the concentration of electric field in this region, prevents dielectric breakdown between the train and gate, and reduces gate junction capacitance. ing. MO of such structure
When manufacturing SFET, you can do it in a short time with fewer steps!
IS is necessary.
第３図は従来の製造方法を説明する断面図を示す。同図
（Ａ）に示す如く、基板１．酸化膜２の表面にポリサイ
ドゲート電極となるポリＳｉ３及び金属シリサイド４を
形成し、更にその表面にレジストパターン５を載置する
。次に、レジストパターン５に従ってエツチングし、そ
の後でレジストパターン５を除去すると、同図（Ｂ）に
示すようなポリＳｉ３と金属シリサイド４とよりなるポ
リサイドのゲート電極６が形成される。FIG. 3 shows a cross-sectional view illustrating a conventional manufacturing method. As shown in FIG. 1A, the substrate 1. PolySi 3 and metal silicide 4, which will become a polycide gate electrode, are formed on the surface of the oxide film 2, and a resist pattern 5 is further placed on the surface. Next, etching is performed according to the resist pattern 5, and then the resist pattern 5 is removed to form a polycide gate electrode 6 made of poly-Si 3 and metal silicide 4 as shown in FIG. 3B.
次に、同図（Ｃ）に示す如（、ゲート電極６の表面にＰ
ＳＧＩ７を形成し、異方性エツチングを行なう。異方性
エツチングは一般に表面から等しい厚さ部分を除去し得
るので、ＰＳＧＩ！７は同図（Ｄ）に示す如く、ゲート
電極６のエツジ部分において上部はど多く除去され、従
って、上部から下部へかけて次第に膜厚が厚くなるよう
な残部７ａが形成される。Next, as shown in FIG.
SGI7 is formed and anisotropic etching is performed. Since anisotropic etching can generally remove equal thickness from a surface, PSGI! As shown in FIG. 7D, a large portion of the upper portion of the edge portion of the gate electrode 6 is removed, thereby forming a remaining portion 7a whose film thickness gradually increases from the upper portion to the lower portion.
次に、同図（Ｅ）に示す如く、残されたＰＳＧ膜残部７
ａを遮蔽としてイオン注入を行なうと、残部７ａに対向
した部分は他の部分に比してイオンのドープかが少なく
なり、これにより、ＬＣＤ化されたドレイン電極８及び
ソース電極９が形成される。Next, as shown in the same figure (E), the remaining PSG film remaining portion 7
When ion implantation is performed with a as a shield, the portion facing the remaining portion 7a is less doped with ions than the other portions, thereby forming a drain electrode 8 and a source electrode 9 that form an LCD. .
上記従来の製造方法は、ＰＳＧ膜７を用いて残部７ａを
形成しなければならないので工程が多くなり、ｙＪ造に
長時間を要する問題点があった。The conventional manufacturing method described above has the problem that the remaining portion 7a must be formed using the PSG film 7, which increases the number of steps and requires a long time for YJ construction.
Ｃ問題点を解決するための手段〕
本発明になるＴＩＩＪ造方法は、第１図に示す如く、上
層部材（金属シリサイド）４の周辺が下履部材（ポリ５
ｉ）３′に対して庇状に突出するように上層部材４を下
履部材３′に比して大ぎくなるようにエツチングしてポ
リサイドゲート電極６′を形成し、上記上層部材４を遮
蔽としてイオン注入を行なってドレイン電極８′及びソ
ース電極９′を形成する。Means for Solving Problem C] In the TIIJ manufacturing method of the present invention, as shown in FIG.
i) Form a polycide gate electrode 6' by etching the upper layer member 4 so as to protrude like an eave from the upper layer member 3' than the lower layer member 3'. Ion implantation is performed as a shield to form a drain electrode 8' and a source electrode 9'.
上層部材（金属シリサイド）４を遮蔽としてイオン注入
を行なうようにしているので、少ない工程でドレイン電
極８′及びソース電極９′を形成し得る。Since ion implantation is performed using the upper layer member (metal silicide) 4 as a shield, the drain electrode 8' and the source electrode 9' can be formed with fewer steps.
（実施例）
第１図は本発明の製造方法の一実施例を説明する断面図
を示す。先ず、同図（Ａ）に示す如く、第３図（Ａ）に
示すものと同様のものを用意し、金属シリサイドのみを
異方性エツチングする。次に、金属シリサイド４には反
応せず、ポリＳｉ３にのみ反応するエツチングガスを用
いて等方性エツチングを行なう。これにより、同図（Ｂ
）に示す如く、金属シリサイド４はレジストパターン５
に従ってこれと同様の大きさにエツチングされるも、ポ
リＳｉ３はレジストパターン５のエツジ部分よりも内側
までエツチングされて金属シリサイド４よりも小さいポ
リＳｉ３’ とされ、金属シリサイド４の周辺には庇部
４ａが形成される。(Example) FIG. 1 shows a cross-sectional view illustrating an example of the manufacturing method of the present invention. First, as shown in FIG. 3(A), a material similar to that shown in FIG. 3(A) is prepared, and only the metal silicide is anisotropically etched. Next, isotropic etching is performed using an etching gas that does not react with the metal silicide 4 but reacts only with the poly-Si3. As a result, the same figure (B
), the metal silicide 4 forms a resist pattern 5.
Accordingly, the poly-Si3 is etched to the same size as this, but the poly-Si3 is etched to the inner side of the edge portion of the resist pattern 5 to form poly-Si3' which is smaller than the metal silicide 4, and an eaves portion is formed around the metal silicide 4. 4a is formed.
次に、レジストパターン５を除去してポリサイドのゲー
ト電極６′を形成し、更に、同図（Ｃ）に示す如く、金
属シリサイド４を遮蔽としてイオン注入を行なうと、金
属シリサイド４の庇部４ａに対向した部分は他の部分に
比してイオンのドープ量が少なくなり、これにより、Ｌ
ＣＤ化されたドレイン電極８′及びソース電極９′が形
成される。Next, the resist pattern 5 is removed to form a polycide gate electrode 6', and ions are implanted using the metal silicide 4 as a shield, as shown in FIG. The portion facing L is doped with less ions than other portions, and this causes L
A CD-shaped drain electrode 8' and source electrode 9' are formed.
このように、本発明では、金属シリサイド４を遮蔽とし
て利用しているので、従来のようにわざわざＰＳＧ膜７
（第３図（Ｃ））を形成しなくてもよく、少ない￥Ｊ造
工程でドレイン電極８′及びソース電極９′を形成し得
る。In this way, in the present invention, since the metal silicide 4 is used as a shield, the PSG film 7 is not used as in the conventional method.
(FIG. 3(C)) is not necessary, and the drain electrode 8' and the source electrode 9' can be formed with a small number of manufacturing steps.
第２図は本発明の製造方法の他の実施例を説明する断面
図を示す。同図（Ａ）に示す状態から先ず異方性エツチ
ングを行ない、同図（８）に示す如く、レジストパター
ン５に従ってこれと同様の大きさのポリＳｉ３及び金属
シリサイド４の構造を形成する。FIG. 2 shows a sectional view illustrating another embodiment of the manufacturing method of the present invention. First, anisotropic etching is performed from the state shown in FIG. 2A to form a structure of poly-Si 3 and metal silicide 4 having the same size as the resist pattern 5, as shown in FIG.
次に、第１図に示す方法と同様に、金属シリサイド４に
は反応せず、ポリＳｉ３にのみ反応するエツチングガス
を用いて等方性エツチングを行ない、同図（Ｃ）に示す
構造（第１図（Ｂ）に示す構造と同じ）を形成する。次
に、同図（Ｄ）に示す如く、金属シリサイド４を遮蔽と
してイオン注入を行なうとドレイン電極８′及びソース
電極９′が形成される。Next, in the same way as the method shown in FIG. 1, isotropic etching is performed using an etching gas that does not react with the metal silicide 4 but only reacts with the poly-Si3, resulting in the structure shown in FIG. 1) is formed. Next, as shown in FIG. 2D, ion implantation is performed using the metal silicide 4 as a shield, thereby forming a drain electrode 8' and a source electrode 9'.
本発明によれば、上層部材を遮蔽としてイオン注入を行
なっているため、従来のようにわざわざＰＳＧ膜のよう
な特別の膜を形成しないでもよく、少ない工程でドレイ
ン電極及びソース電極をＬＤＤ化し得る等の特長を有す
る。According to the present invention, since ion implantation is performed using the upper layer member as a shield, there is no need to take the trouble to form a special film such as a PSG film as in the past, and the drain electrode and source electrode can be converted to LDD with fewer steps. It has the following features.
第１図は本発明方法の一実施例を示す断面図、第２図は
本発明方法の他の実施例を丞す断面図、第３図は従来方
法の一例を示す断面図である。
図中において、
１は基板、
２は酸化膜、
３．３′はポリＳｉ（下履部材）
４は金属シリサイド（上層部材）
４ａは庇部、
５はレジストパターン、
６′ はポリｔイドゲート電極、
８′はドレイン電極、
９′はソース電極である。
−こFIG. 1 is a cross-sectional view showing one embodiment of the method of the present invention, FIG. 2 is a cross-sectional view of another embodiment of the method of the present invention, and FIG. 3 is a cross-sectional view showing an example of the conventional method. In the figure, 1 is the substrate, 2 is the oxide film, 3.3' is poly-Si (shoe member), 4 is metal silicide (upper layer member), 4a is the eave part, 5 is the resist pattern, and 6' is the poly-tide gate electrode. , 8' is a drain electrode, and 9' is a source electrode. -ko
Claims (1)
に突出するように該上層部材（４）を該下履部材（３′
）に比して大きくなるようにエッチングしてポリサイド
ゲート電極（６′）を形成し、上記上層部材（４）を遮
蔽としてイオン注入を行なつてドレイン電極（８′）及
びソース電極（９′）を形成することを特徴とする半導
体装置の製造方法。The upper layer member (4) is attached to the lower layer member (3') so that the periphery of the upper layer member (4) projects like an eave relative to the lower layer member (3').
) is etched to form a polycide gate electrode (6'), and ions are implanted using the upper layer member (4) as a shield to form a drain electrode (8') and a source electrode (9'). ') A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15293886A JPS639154A (en) | 1986-06-30 | 1986-06-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15293886A JPS639154A (en) | 1986-06-30 | 1986-06-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639154A true JPS639154A (en) | 1988-01-14 |
Family
ID=15551430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15293886A Pending JPS639154A (en) | 1986-06-30 | 1986-06-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639154A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5413295A (en) * | 1991-08-09 | 1995-05-09 | Heiwa Seiki Kagya Co., Ltd. | Weight balancer for tripod head |
| US6624473B1 (en) * | 1999-03-10 | 2003-09-23 | Matsushita Electric Industrial Co., Ltd. | Thin-film transistor, panel, and methods for producing them |
-
1986
- 1986-06-30 JP JP15293886A patent/JPS639154A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5413295A (en) * | 1991-08-09 | 1995-05-09 | Heiwa Seiki Kagya Co., Ltd. | Weight balancer for tripod head |
| US5415254A (en) * | 1991-08-09 | 1995-05-16 | Heiwa Seiki Kagya Co., Ltd. | Panning braking device for tripod head |
| US5419520A (en) * | 1991-08-09 | 1995-05-30 | Heiwa Seiki Kogyo Co., Ltd. | Tripod head |
| US6624473B1 (en) * | 1999-03-10 | 2003-09-23 | Matsushita Electric Industrial Co., Ltd. | Thin-film transistor, panel, and methods for producing them |
| US6812490B2 (en) | 1999-03-10 | 2004-11-02 | Matsushita Electric Industrial Co., Ltd. | Thin-film transistor, panel, and methods for producing them |
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