JPS6390222A - Modulating circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction in a reception-side equipment by always surely keeping the level of an output signal in a mark or space state when each transmission of a modulated signal is terminated. CONSTITUTION:A signal TxEN/rises at a timing (f) in the figure at the time of the end of data transmission. Since one input of a NOR circuit 18 goes to a high level then, an output signal (a) is kept in a low level thereafter, and a FF 12 which determines the bit cell timing is inverted no more. Since the change of a signal (b) causes the change of signals in the bit cell section of a transmission signal DMiD, a signal (d) outputted from an exclusive OR circuit 17 is not changed at the last bit cell timing (k), namely, timing (j) if the signal (b) is not changed from timing (i). Consequently, the input signal (d) at timing (n) has the same level as the input signal (d) set at timing l in a FF 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to DMI (different
ntial mark 1nversion), etc.

[Prior Art] When transmitting digital image data, it has been proposed to modulate the data in order to ensure reliable transmission and reception. One such modulation method is the so-called DMI modulation method, which performs a modulation operation using data and a clock. In this DMI modulation method, it is necessary to hold the signal in either a mark or a space while data is not being transmitted.

On the other hand, in order to execute such modulation processing at high speed, it is common to configure the modulation circuit with a hardware circuit, but due to the time delay at the rise/fall of the hardware circuit, the final Spike noises could occur where there should be marks or spaces.

[Problems to be Solved by the Invention] The present invention eliminates the above-mentioned drawbacks of the prior art, and its purpose is to ensure that the output signal level is always marked or The object of the present invention is to provide a modulation circuit that is maintained in a state of space.

[Means for Solving the Problems] In order to achieve the above object, the modulation circuit of the present invention includes a flip-flop circuit that determines the bit cell timing of data by inverting the level at a predetermined period, and a flip-flop circuit that determines the bit cell timing of data by inverting the level at a predetermined period. an NRZ conversion circuit that performs NRZ conversion on transmission data with a phase shift, and modulation that modulates the transmission data by taking an exclusive OR of a bit cell timing signal output from the flip-flop circuit and an NRZ data signal output from the NRZ conversion circuit. and an inversion prevention circuit that prevents the output of the flip-flop circuit from being inverted after the last bit cell timing in response to a data transmission end signal.

[Operation] In this configuration, the flip-flop circuit determines the bit cell timing of data by inverting the level at a predetermined period. On the other hand, the NRZ conversion circuit performs NRZ conversion on the transmission data with a 172 phase shift from the bit cell timing. The modulation circuit modulates the transmission data by exclusive ORing the bit cell timing signal output from the flip-flop circuit and the NRZ data signal output from the NRZ conversion circuit. The inversion prevention circuit prevents the flip-flop circuit output from being inverted after the last bit cell timing in response to the data transmission end signal.

[Examples] Examples of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of the DMI modulation circuit of the embodiment, and the second
FIG. 1 is a timing chart showing the operation of the DMI modulation circuit shown in FIG. In FIG. 1, 11 to 15 are D-type flip-flops (FF), 16 and 17 are exclusive OR circuits, and 18 is a NOR circuit. Also TxE
N/ is a transmittable signal, CLK is a clock signal, TXc/
(/ indicates negative logic) is a transmission clock signal, TXD is transmission data, and DMiD is a modulated transmission signal.

The clock signal CLK is frequency-divided by 1/2 by the FF 14 to become the transmission clock signal TxC/. The transmission clock signal Tx
The falling edge of C/ is synchronized with each data bit cell of the transmission data TxD. Transmission data T in Figure 2
Parts (A) and (B) of XD correspond to two consecutive data bit cells of the last part of the series of transmitted data.

The FFII sets the input transmit enable signal TxEN/ at the timing of each rising edge of the transmission clock signal "rxC/. Therefore, it outputs the signal ■ which is delayed by one bit cell from the input. This signal ■ indicates the end of each data transmission. HI at times
GH level, and this HI G, H level is FF15
Since this is forcibly set, this DMI modulation circuit always holds the mark level while not transmitting data.

The FF 12 receives the transmission clock signal "rxC/" from the NOR circuit 18 whose other input is the transmission enable signal TxEN/.
The clock input is the inverted signal ■ of
Outputs a signal ■ that is inverted.

The FF 13 uses the transmission clock signal TxC/ as a clock, and converts the transmission data signal TxD into an NRZ signal at each rising edge of the clock signal TxC/. That is, when the transmission data signal TxD becomes LOW level (logical O) or while it is at LOW level, the output of the FF 13 is held at the same level, and when the transmission data signal TXD is HIGH.
When the level (logic 1) is reached, the output level of FF13 is inverted, and while the transmission data signal TxD is at the )ilGH level, the output level of FF13 is inverted in synchronization with each rising edge of the clock signal 'rxC/. .

This is the signal ■ in FIG.

FFI 5 is a transmission signal DM obtained by DMI modulating the NRZ signal.
Form an ID. That is, the exclusive jib OR circuit 17
Since the circuit 17 receives the signals ■ and ■ as input, the signal ■ is obtained as the output of the circuit 17 . The signal @ is a signal that does not change between each bit cell because the output of the FF 13 is not inverted while the transmission data signal TXD is at the LOW level. FF15
sets the signal ■ at each rising edge of the clock signal CLK.

Then, at the end of data transmission, the signal TxEN/ rises at timing f in the figure. As a result, one input of the NOR circuit 18 becomes HIGH level, so its output signal ■
is then kept at a LOW level, and FF12, which determines the bit cell timing, is no longer inverted. That is, F
The output signal (■) of F12 does not rise even at timing i.

Since the change in the signal (2) produces a change in the signal in the bit cell section of the transmission signal DMiD, when this signal stops changing at the last timing of the final transmission bit cell, that is, at the timing i, the exclusive-Jib OR circuit 17 output Even in the signal ■, no change occurs at the end of the final bit cell timing, that is, at the timing j. Therefore, in the FF 15, the input signal ■ at timing n has the same level as the input signal ■ set at timing λ, so the clock setting operation at timing n does not cause a change in the D Mi D signal. In this way, the output signal level at the end of transmission of the DMI modulated signal is reliably maintained at the mark state. Although the data patterns of the transmitted data signal TxD vary, the above-described operation applies to any data pattern, so that the DMiD signal is stably and reliably held at the mark level (or space level) at the end of each data transmission.

[Effects] As described above, according to the present invention, the output signal level is always reliably maintained in the mark or space state at the end of each transmission of the modulated signal, thereby preventing malfunctions in the receiving device.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the DMI modulation circuit of the embodiment, and FIG. 2 is a timing chart showing the operation of the DMI modulation circuit of FIG. 1. In the figure, 11 to 15...D type flip-flop (F
F), 16.17... exclusive jib OR circuit, 1
8...NOR circuit.

Claims (1)

[Claims] A modulation circuit that maintains a signal at either mark or space level while not transmitting data includes a flip-flop circuit that determines data bit cell timing by inverting the level at a predetermined period; /2 phase shift and send data to NR
an NRZ conversion circuit that performs Z conversion; a modulation circuit that modulates the transmission data by taking an exclusive OR of the bit cell timing signal output from the flip-flop circuit and the NRZ data signal output from the NRZ conversion circuit; and a modulation circuit that modulates the transmission data. A modulation circuit comprising an inversion prevention circuit that prevents inversion of the output of the flip-flop circuit after the last bit cell timing based on a signal.