JP2007006060A - Integrated circuit, reproducing apparatus, and reproducing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correctly reproduce data even if a duty ratio changes from 50% under such condition as clock frequency varies by applying, for example, a non-contact IC card system, relating to an integrated circuit, reproducing apparatus, and reproducing method. <P>SOLUTION: Operation of a PLL circuit is switched for faster convergence compared with part of payload, and reference signals are phase-controlled so that one of the reference signals of different phase by 90° is synchronized for phase with an input signal. When a result of phase comparison that the other reference signal is synchronized for phase with the input signal is obtained, a previous control is continued. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an integrated circuit, a reproducing apparatus, and a reproducing method, and can be applied to, for example, a non-contact type IC card system. The present invention switches the operation of the PLL circuit so that it converges faster than the payload portion, and controls the phase of these reference signals so that one of the reference signals having a phase difference of 90 degrees is phase-synchronized with the input signal. When the phase comparison result that the other reference signal is phase-synchronized with the input signal is obtained, the duty ratio changes from 50 [%] with the clock frequency varying by continuing the previous control. Even if it does, it will be possible to reproduce the data correctly.

  Conventionally, an IC card system using a non-contact type IC card is formed by an IC card possessed by each user, a reader / writer that transmits and receives various data to and from each IC card, etc. It is used for systems.

  Here, the reader / writer generates a carrier signal having a frequency of 13.56 [MHz], for example, and transmits the carrier signal from the antenna. As a result, the reader / writer sends power for operation to the IC card. The reader / writer generates a clock by dividing the carrier signal, operates based on the clock, and modulates the amplitude of the carrier signal transmitted from the antenna by data used for transmission. As a result, the reader / writer sends various data to the IC card by radio communication waves sent from the antenna.

  On the other hand, the IC card generates a power supply for operation by receiving a radio communication wave transmitted from the reader / writer with an antenna and rectifying and smoothing it. Also, the radio communication wave that is operated by the power supply for operation and received by the antenna is processed by a PLL (Phase Locked Loop) circuit to regenerate the clock, and further, by processing of the radio communication wave based on the regenerated clock Various data sent from the reader / writer are received.

  Further, the IC card is operated by the clock by the PLL circuit, updates the data held in the built-in memory according to the received data, and further sends various data to the reader / writer. The IC card executes the transmission of data to such a reader / writer by switching the terminal impedance of the antenna depending on the data used for transmission.

  Here, when the terminal impedance of the antenna is switched on the IC card side in this way, on the reader / writer side, the impedance of the antenna changes due to the mutual inductive action, thereby changing the signal level of the carrier signal applied to the antenna. Thus, the reader / writer processes the carrier signal by the PLL circuit to reproduce the clock, and further reproduces the data sent from the IC card by signal processing using the reproduced clock.

  In such an IC card system, a clock is regenerated using a PLL circuit using a technique disclosed in Japanese Patent Laid-Open No. 11-274929.

  That is, as shown in FIG. 12, the PLL circuit according to the conventional IC card divides the carrier signal of the received radio communication wave by a predetermined frequency division ratio and has two systems with different phases depending on the clock frequency by 90 degrees. Signals I and Q (FIGS. 12A and 12B) are generated. In the following, in the reference signals I and Q whose phases are different by 90 degrees, the reference signal I having a 90-degree advance phase is called an I arm, and the rest is called a Q arm. One period of the I arm is divided into four periods by switching the signal levels of the I arm and the Q arm. In the following, each period is referred to as a phase. FIG. 12 shows a case where the Q arm Q thus generated is phase-synchronized with the input signal IN.

  The PLL circuit receives a binary signal IN obtained by binarizing the radio communication wave obtained from the antenna and binarizing the detection result. The PLL circuit receives the binary signal IN and the I arm I. Is generated by an exclusive OR circuit, and the phase comparison result between the input signal IN and the I arm I is detected. Similarly, an exclusive OR signal between the input signal IN and the Q arm Q is generated by an exclusive OR circuit, and thereby the phase comparison result between the input signal IN and the Q arm Q is detected.

  The PLL circuit switches between the signal level at the I arm I and the point approximately halfway between the signal level at the Q arm Q and the signal level at the Q arm Q. A sampling signal SP whose signal level rises at a substantially middle point in time until the signal level is switched is generated, and exclusive OR signals by the I arm I and the Q arm Q are sampled by the sampling signal SP, respectively. . As a result, the PLL circuit acquires the phase comparison result for each phase.

  If the sampling results EX1I and EXQ (FIGS. 12E and 12F) (FIGS. 12E and 12F) obtained by the exclusive OR obtained in this way are totaled by one period of the I arm I or Q arm Q, as shown in FIG. The total value ΣEXI relating to the I arm I becomes 0 when the phase of the I arm I matches the phase of the input signal IN, and the phase of the I arm I is 180 degrees different from the phase of the input signal IN. If it is, the value is 4. If the phase is 90 degrees, the value is 2. The total value ΣEXQ relating to the Q arm Q is 2 when the phase of the I arm I matches the phase of the input signal IN, and when the phase of the I arm I is 180 degrees different from the phase of the input signal IN. It becomes. The value is 0 when the phase of the I arm I is 90 degrees ahead of the phase of the input signal IN, and the value is 4 when the phase of the I arm I is 90 degrees behind the phase of the input signal IN. As a result, the current phase of the I arm I or Q arm Q with respect to the input signal IN can be determined from the values of the total values ΣEXI and ΣEXQ.

  Thereby, the PLL circuit calculates and determines these total values ΣEXI and ΣEXQ by a predetermined period of the I arm, and increases or decreases the frequency dividing ratio of the frequency dividing circuit used for generating the reference signals I and Q according to the determination result. In FIG. 13, the phases of the I arm I and the Q arm Q are changed in the direction indicated by the arrows, and the I arm I is synchronized with the input signal IN.

  Specifically, as shown in FIG. 14, the PLL circuit according to the conventional IC card detects the phase control directions for the I arm I and the Q arm Q by determining the total values ΣEXI and ΣEXQ, respectively, The control direction was comprehensively determined to control the phases of the I arm I and the Q arm Q. Here, the symbols + and − are controls for setting the phases of the I arm I and the Q arm Q to be the advance phase and the delay phase, respectively, and the symbol 0 is a case where the phase is not controlled.

  By the way, this kind of IC card system is provided that the function of the IC card can be used also in the mobile phone by providing the configuration related to the IC card in the mobile phone. Specifically, when the IC card configuration is provided in the mobile phone in this way, an electronic money system or the like based on the IC card system can be used by the mobile phone.

  In this way, when an IC card configuration is provided in a mobile phone, an active IC that is difficult to achieve with this type of IC card, which is passive, if the configuration related to the IC card is driven by the power supply of the mobile phone and the carrier signal. Various functions related to the card can be realized. That is, in this case, the mobile phone generates a carrier signal for the IC card from the configuration related to the mobile phone, and generates a clock for the IC card from the carrier signal for the IC card. Also, with the configuration related to the IC card, an amplitude modulated wave is generated from the carrier signal and clock for the IC card, and this amplitude modulated wave is sent out from the antenna related to the IC card. In this way, the reader / writer can be activated by calling from the mobile phone side to send and receive various data, and further, various data can be sent and received between the same type of mobile phones by the function of the IC card. .

  However, some mobile phones generate a clock using a ceramic oscillator, and the frequency deviation of the output signal of a clock generated by a ceramic oscillator is smaller than when a clock is generated using a crystal oscillator. There are major drawbacks. Thus, in a mobile phone configured to generate a clock using a ceramic oscillator as described above, when a carrier signal having a frequency of 13.56 [MHz] related to an IC card is generated using the configuration of the mobile phone, The frequency of the signal varies in the frequency range of 13.41 to 13.71 [MHz]. If the frequency of the carrier signal varies as described above, the frequency varies accordingly even in the operation clock of the IC card created by dividing the carrier signal.

If the frequency of the operation clock varies as described above, it takes time to lock the PLL circuit on the receiving side such as a reader / writer, and there is a possibility that data cannot be reproduced correctly. In particular, in this type of system, the distance between communication objects may change, and when the distance between communication objects changes in this way, the duty ratio of received data changes greatly from 50 [%]. In the conventional PLL circuit, when the duty ratio changes in this manner with the clock frequency varied, it is difficult to correctly reproduce the clock by the PLL circuit, and thus it is difficult to correctly reproduce the data. There was a problem.
JP 11-274929 A

  The present invention has been made in consideration of the above points. An integrated circuit and a reproducing apparatus capable of correctly reproducing data even when the duty ratio is changed from 50% in a state where the clock frequency varies. And a reproduction method.

  In order to solve this problem, the invention of claim 1 is applied to an integrated circuit that regenerates a clock from a binarized signal obtained by binarizing a detection signal of a radio communication wave obtained by an antenna. A reference signal generation circuit for generating an I arm and a Q arm as signals, and a phase comparison for the I arm that compares the phase of the I arm and the binary signal and outputs a phase comparison result for the I arm A phase comparison circuit relating to the Q arm for outputting a phase comparison result relating to the Q arm by comparing the phase of the circuit, the Q arm and the binarized signal, and the phase comparison result relating to the I arm and the Q A control circuit that changes the phases of the I arm and the Q arm by controlling the reference signal generation circuit based on the phase comparison result of the arm, and synchronizes the phase of the I arm with the binarized signal. The I arm or Q arm is set to the clock, and the control circuit controls the operation of the reference signal generation circuit according to a certain period in the I arm, and the preamble in the binarized signal Compared to the payload portion of the binary signal, the fixed period is shortened, and the phase synchronization result of the Q arm detects the phase synchronization of the Q arm to the binary signal based on the phase comparison result of the Q arm. Then, the reference signal generation circuit is controlled in the same manner as the control of the reference signal generation circuit in the immediately preceding fixed period.

  The invention of claim 9 is applied to a reproducing apparatus that reproduces data transmitted by a radio communication wave, generates a detection signal of the radio communication wave, binarizes the detection signal, and generates a binarized signal. The RF circuit to be generated, the reference signal generation circuit that generates the I arm and the Q arm, which are reference signals that are 90 degrees out of phase, the I arm and the binarized signal are phase-compared, and the I arm A phase comparison circuit for the I arm that outputs a phase comparison result, a phase comparison circuit for the Q arm that compares the phase of the Q arm and the binarized signal, and outputs the phase comparison result of the Q arm; The phase of the I arm and the Q arm is changed by the control of the reference signal generation circuit based on the phase comparison result related to the I arm and the phase comparison result related to the Q arm, and the I arm is changed to the binary signal. Position A control circuit for synchronizing, and a demodulating circuit for processing the binarized signal by the I arm or Q arm to reproduce the data, wherein the control circuit is configured to generate the reference signal according to a certain period in the I arm. In the preamble of the binarized signal, the constant period is shortened compared to the payload portion of the binarized signal, and the preamble is determined based on the phase comparison result related to the Q arm. When the phase synchronization of the Q arm to the binary signal is detected, the reference signal generation circuit is controlled in the same manner as the control of the reference signal generation circuit in the immediately preceding fixed period.

  The invention of claim 10 is applied to a reproduction method for reproducing data transmitted by a radio communication wave, generates a detection signal of the radio communication wave, binarizes the detection signal, and converts the binarized signal to A phase comparison is performed between the step of generating a binary signal to be generated, the step of generating a reference signal for generating an I arm and a Q arm, which are reference signals having a phase difference of 90 degrees, The phase comparison step for the I arm that outputs the phase comparison result for the I arm, the phase comparison of the Q arm and the binarized signal, and the output of the phase comparison result for the Q arm The phase of the I arm and the Q arm is changed by controlling the reference signal generation circuit based on the phase comparison step for the arm and the phase comparison result for the I arm and the phase comparison result for the Q arm. A control step of phase-synchronizing the I arm with the binarized signal, and a demodulating step of processing the binarized signal by the I arm or Q arm to reproduce the data. The step of obtaining a phase comparison result related to the I arm and a phase comparison result related to the Q arm according to a certain period in the I arm, controlling the operation of the reference signal generation circuit, and binarizing In the preamble of the signal, the constant period is shortened compared to the payload portion of the binarized signal, and the binarization of the Q arm in the preamble is based on the phase comparison result related to the Q arm. When phase synchronization with a signal is detected, the reference signal generation circuit is controlled in the same manner as the control of the reference signal generation circuit in the immediately preceding fixed period.

  According to the configuration of claim 1, when applied to an integrated circuit that regenerates a clock from a binarized signal obtained by binarizing a detection signal of a radio communication wave obtained by an antenna, an I arm that is a reference signal having a phase difference of 90 degrees and A reference signal generation circuit for generating a Q arm, a phase comparison circuit for the I arm that compares the phase of the I arm and the binarized signal and outputs a phase comparison result for the I arm, and the Q arm And the binarized signal are phase-compared to output a phase comparison result relating to the Q arm, a phase comparison circuit relating to the Q arm, a phase comparison result relating to the I arm, and a phase comparison result relating to the Q arm A control circuit that changes the phase of the I arm and the Q arm by controlling the reference signal generation circuit according to the above, and synchronizes the phase of the I arm with the binarized signal. The arm is set to the clock, and the control circuit controls the operation of the reference signal generation circuit according to a certain period in the I arm, and in the preamble of the binary signal, the payload of the binary signal If the fixed period is shortened as compared with the part of (1), the I arm can be phase-synchronized with the binarized signal at a higher speed by the amount of the control period set shorter in the preamble. Even when the frequency varies, it is possible to reliably reproduce the clock and reproduce the data correctly. However, in such control, the Q arm may be phase-synchronized with the binarized signal. In this case, which side should be controlled in the leading phase direction or the lagging phase direction? It cannot be determined depending on the phase comparison result. Thus, if the phase is not changed at all, it takes time for phase synchronization, and in some cases, data cannot be correctly reproduced. Further, if the phase is forcibly changed in any direction, the control direction is frequently switched when the duty ratio of the binarized signal is changed from 50 [%]. There are cases where synchronization takes time. Thus, when phase synchronization of the Q arm to the binarized signal is detected in the preamble based on the phase comparison result of the Q arm, the control of the reference signal generation circuit in the immediately preceding fixed period is performed. Similarly, if the reference signal generation circuit is controlled, the phase of the I arm can be changed in a substantially correct direction, and the duty ratio is changed from 50% in a state where the frequency of the carrier signal varies. Even in such a case, it is possible to reproduce the clock correctly by reliably reproducing the clock.

  Thus, according to the configuration of claim 9 or claim 10, a reproducing apparatus and a reproducing method capable of reproducing data correctly even when the duty ratio changes from 50 [%] in a state where the clock frequency varies. Can be provided.

  According to the present invention, data can be correctly reproduced even when the duty ratio changes from 50 [%] while the clock frequency varies.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 1 is a block diagram showing an IC card system according to an embodiment of the present invention. The IC card system 11 transmits and receives various data between the reader / writer 12 and the IC card 13 by bringing the IC card 13 closer to the reader / writer 12, thereby executing a series of processes related to electronic money and the like. To do. In addition, by bringing the mobile phone 14 closer to the reader / writer 12, various data are transmitted and received between the reader / writer 12 and the mobile phone 14, thereby similarly executing a series of processes relating to electronic money and the like.

  For this reason, the IC card 13 is configured in the same way as an IC card having a conventional configuration, receives a radio communication wave transmitted from the reader / writer 12 through a built-in antenna, and starts operation by a power source using the radio communication wave. Further, the operation is started in this manner, and the clock is reproduced from the built-in PLL circuit from the wireless communication wave, and the data transmitted from the reader / writer 12 is reproduced by the processing of the wireless communication wave using this clock. Further, the contents of the built-in memory are updated with the reproduced data, and various data are sent to the reader / writer 12.

  The mobile phone 14 is formed by adding a configuration related to an IC card to a normal mobile phone. That is, in the mobile phone 14, the mobile phone unit 16 executes a series of processes related to calls, e-mails, and the like under the control of the controller 15 in response to an operation by the user, and the controller 15 responds to the operation by the user. The operation of each part of the mobile phone 14 is controlled.

  Similar to the IC card 13, the IC card unit 17 receives a wireless communication wave transmitted from the reader / writer 12 through a built-in antenna, and starts operation by a power source using the wireless communication wave. Further, the operation is started in this manner, and the clock is reproduced from the built-in PLL circuit from the wireless communication wave, and the data transmitted from the reader / writer 12 is reproduced by the processing of the wireless communication wave using this clock. Further, the contents of the built-in memory are updated with the reproduced data, and various data are sent to the reader / writer 12. As a result, the mobile phone 14 executes a series of processes related to electronic money or the like by an independent function of the IC card unit 17.

  Further, in this embodiment, the IC card unit 17 operates as an active IC card under the control of the controller 15 and transmits various data to the reader / writer 12 and the same type of mobile phone. That is, in this case, the IC card unit 17 starts to operate with the power supply of the mobile phone unit 16, and the carrier with the frequency of 13.56 [MHz] is generated from various reference signals generated by using the ceramic oscillator in the mobile phone unit 16. The signal S1 is input. The carrier signal S1 is divided to generate an operation clock. The IC card unit 17 operates by this operation clock to modulate the amplitude of the carrier signal S1, and sends out the resulting amplitude modulated signal from the antenna. As a result, the cellular phone 14 functions as an active IC card, and transmits / receives various data to / from the reader / writer 12 and further to the same type of cellular phone. As described above, the mobile phone 14 transmits and receives various data to and from the same type of mobile phone by the function of the IC card, so that the IC card unit 17 of the mobile phone 14 is similar to the reader / writer 12 described later. The RF transceiver circuit 21 and the data processing circuits 20 and 22 are provided so that data can be correctly reproduced even when the duty ratio is changed from 50 [%] with the clock frequency varying. Configured as follows.

  FIG. 2 is a chart showing the format of data sent from the IC card unit 17 when operating as an active IC card. Here, this data format is formed by the order of a 3-byte preamble, a 2-byte sync, a length LEN indicating the data length of the payload, and the payload. Here, the preamble is set with data having a value of 00, and the sync is set with data having a value b2 and a value 4d. The payload is set so that a maximum of 257 bytes of data can be allocated. In this case, the length LEN is set to the value FF.

  The IC card unit 17 generates serial data in the format shown in FIG. 2 using a Manchester code, and modulates and transmits the carrier signal S2 with the transmission data signal based on the serial data. Here, the Manchester code is a code in which logic 1 and logic 0 are set to opposite polarities and the signal level is inverted at the center of each bit.

  The reader / writer 12 is configured to correspond to the configuration of such a communication target, and transmits / receives various data to / from the IC card 13 and the mobile phone 14. Here, the reader / writer 12 has a data processing circuit 22 for correcting the duty ratio and frequency deviation of the transmission data signal S4 received by the RF transmission / reception circuit 21 in the reception system between the data processing circuit 20 and the RF transmission / reception circuit 21. It is formed by insertion. In the following description, the transmission data signal by Manchester code received by the reader / writer or the like is obtained by binarizing the radio communication wave obtained from the antenna and then appropriately 2 This is called a value signal.

  Here, the data processing circuit 20 is an integrated circuit that constitutes a reader / writer together with the RF transmission / reception circuit 21 in a passive IC card system, and controls the overall operation by executing processing procedures recorded in a memory (not shown). Then, a series of processes related to electronic money and the like are executed, and data to be transmitted is output to the RF transmission / reception circuit 21 by Manchester code, and the received data is input and decoded.

  That is, in this series of processing, the data processing circuit 20 separates the carrier signal S2 having a frequency of 13.56 [MHz] generated by a crystal oscillation circuit (not shown) when sending data to the IC card 13, the mobile phone 14, or the like. To generate an operation clock. Further, a transmission data signal S3 is generated using the Manchester code having the format described above with reference to FIG. Here, in this case, the leading preamble is set to 6 bytes. Further, according to the output of the transmission data signal S3, the setting of the carrier output timing signal / RFON and the data transmission timing signal RFTRA output to the data processing circuit 22 is switched. Here, the carrier output timing signal / RFON is a timing signal for instructing the RF transmission / reception circuit 21 to output a carrier signal, and the data transmission timing signal RFTRA is RF modulation of the carrier signal transmitted from the antenna by the transmission data signal S3. This is a timing signal for instructing the transmission / reception circuit 21.

  On the other hand, when data is transmitted in this way and data related to a response is received from the IC card 13, the mobile phone 14, etc., in a state where the carrier signal is set to be transmitted from the RF transceiver circuit 21, The data processing circuit 20 switches the setting of the data transmission timing signal RFTRA, thereby setting the entire operation to the data reception state. In this state, the clock is reproduced from the received data CDRIO output from the data processing circuit 22 in the form of Manchester code, and the received data CDRIO is processed by this clock, and the data sent from the IC card 13 and the mobile phone 14 is processed. Decrypt. The data processing circuit 20 executes, for example, a series of processes related to electronic money with the IC card 13 and the mobile phone 14 by repeating this series of processes.

  On the other hand, when the cellular phone 14 functions as an active IC card and receives data transmitted from the cellular phone 14, the data processing circuit 20 switches the setting of the carrier output timing signal / RFON, thereby Transmission of the carrier signal from the RF transmission / reception circuit 21 is stopped. In this state, similarly to the case of receiving data from the communication target by the passive type described above, the clock is reproduced from the received data CDRIO output from the data processing circuit 20, and the received data CDRIO is processed by this clock to carry the data. Data transmitted from the telephone 14 is decrypted. When the mobile phone 14 functions as an active IC card and receives data transmitted from the mobile phone 14 in this way, the carrier signal may be continuously output. In this case, the mobile phone 14 On the side, data may be sent by switching the terminal impedance based on the clock generated by the built-in ceramic resonator, and the carrier signal generated by the built-in ceramic resonator Amplitude modulation may be performed by a transmission data signal using a clock generated by the frequency division.

  As a result, the data processing circuit 20 is provided with a PLL circuit or the like so that the binarized signal S4 from the RF transmission / reception circuit 21 is directly input to the reception data input terminal CDRI for inputting data from the data processing circuit 22 and processed. Thus, in such a system in which the frequency deviation of the carrier signal is small, the reader / writer can be configured by omitting the data processing circuit 22.

  The data processing circuit 20 executes such a series of data transmission / reception at a data transfer rate of 212 [kbps] according to the program recorded in the memory, and the communication target is set to 424 [kbps] by this data transmission / reception. When the data transfer rate is confirmed, the baud rate setting signal BAUDR is switched, and the data processing circuit 22 is instructed to reproduce data at a data transfer rate of 424 [kbps]. Further, the frequency dividing ratio for generating a clock from the carrier signal S2 is switched, and thereby the data transfer rate of the transmission data signal S3 transmitted to the RF transmitting / receiving circuit 21 is switched from 212 [kbps] to 424 [kbps]. Further, the setting relating to the processing of the received data CDRIO input from the data processing circuit 22 is switched, and thereby the operation is switched so that the received data can be processed at 424 [kbps]. Thus, in this embodiment, the data transfer speed is switched to a high speed according to the communication target by negotiation with the communication target.

  Further, the data processing circuit 20 outputs to the data processing circuit 22 a mode switch CLKOEN for data output from the data processing circuit 22, a reception reset RECCLR by software instructing forcible initialization of the processing being received, and the like.

  The inverter 24 inverts the carrier output timing signal / RFON, and outputs a reception reset / RESET instructing the data processing circuit 22 to reset to the initial state by hardware.

  The RF transmission / reception circuit 21 transmits the transmission data signal S3 output from the data processing circuit 20 to the IC card 13 and the mobile phone 14 under the control of the data processing circuit 20 and received from the IC card 13 and the mobile phone 14. The value signal (transmission data signal) S4 is output to the data processing circuit 22.

  That is, the RF transmitter / receiver circuit 21 outputs the carrier signal S2 to the antenna 25 at the falling edge of the carrier output timing signal / RFON, thereby sending the operation power to the passive IC card 13 and the mobile phone 14. Further, the RF transmission / reception circuit 21 modulates the amplitude of the carrier signal S2 output from the antenna 25 by the data transmission timing signal RFTRA by the transmission data signal S3 output from the data processing circuit 20, and is thus transmitted from the data processing circuit 20. Data is output to the IC card 13 and the mobile phone 14. Further, the RF transmission / reception circuit 21 detects the carrier signal applied to the antenna 25 at the rising edge of the data transmission timing signal RFTRA, and binarizes the detection signal that is the detection result to generate a binary signal. As a result, the transmission data signal S4 transmitted from the IC card 13 and the mobile phone 14 is reproduced and output by mutual induction with the antenna provided on the IC card 13 and the mobile phone 14.

  On the other hand, when receiving data from a communication target operating by the active type, the RF transmission / reception circuit 21 stops applying the carrier signal S2 to the antenna 25 by the carrier output timing signal / RFON. Further, at the rise of the data transmission timing signal RFTRA, the radio communication wave received by the antenna 25 is detected by the envelope detection, and the detection result is binarized to generate a binarized signal. Thereby, the RF transmission / reception circuit 21 reproduces and outputs the transmission data signal S4 transmitted from the mobile phone 14.

  As a result, in this embodiment, even when the mobile phone 14 is operating in an active mode, when the data is transmitted from the reader / writer 12, the carrier signal S1 is amplitude-modulated from the reader / writer 12 to the data processing circuit 20. The binary signal S3 from the data processing circuit 20 is switched from the data processing circuit 20 by switching the terminal impedance of the antenna 25 as in the case of the IC card 13 operating by the active type. May be sent out.

  FIG. 3 is a block diagram showing a configuration of the data processing circuit 22. The data processing circuit 22 is an integrated circuit inserted in a receiving system between the data processing circuit 20 and the RF transmission / reception circuit 21 in a system in which the frequency deviation of a carrier signal transmitted from a transmission target is large by using a ceramic oscillation element or the like. It is. The data processing circuit 22 corrects and outputs the duty ratio and frequency deviation in the binarized signal S4 output from the RF transmission / reception circuit 21.

  That is, in the data processing circuit 22, the clock generation reset circuit 31 receives and divides the carrier signal S2 (CLKIN), and generates an operation reference signal for each part. In this process, the clock generation reset circuit 31 switches the frequency division ratio according to the baud rate setting BAUDR, and thereby generates an operation reference signal for each part at a frequency according to an instruction from the data processing circuit 20. In addition, a counter used to generate the operation reference signal is initialized by reception resets RECCLR and / RESET, and further, a reset signal is output to each unit to initialize settings of each unit.

  The terminal setting register 32 records and holds various settings such as the baud rate setting BAUDR, and notifies each unit of the held contents. As a result, the terminal setting register 32 switches the setting of the data processing circuit 22.

  The PLL circuit 33 regenerates a clock from the binarized signal S4 output from the RF transceiver circuit 21, demodulates the binarized signal S4 with reference to the regenerated clock, and outputs received data D1 based on the demodulation result. To do. At this time, the PLL circuit 33 generates I arm I and Q arm Q, which are two kinds of reference signals having a phase difference of 90 degrees, with a duty ratio of 50 [%]. The phase of the I arm I and Q arm Q is changed according to the phase comparison result with a certain binarized signal S4, and thereby the I arm I is phase-synchronized with the binarized signal S4 to reproduce the clock.

  That is, as shown in FIGS. 4 and 5, in the PLL circuit 33, when the reference signal generation circuit 34 processes the binarized signal S4 with a transmission rate of 212 [kbps], the division ratio is 16 in the initial state. And the carrier signal S2 is frequency-divided by this ring counter to generate the I arm I and the Q arm Q (FIGS. 5A and 5B). The reference signal generation circuit 34 generates and outputs a sampling signal SP1 by logical operation of the I arm I and Q arm Q and the carrier signal S2. Here, in this embodiment, the sampling signal SP1 is generated so that the signal level rises before and after the switching of each signal level in the I arm I and the Q arm Q (FIG. 5D), thereby each phase. Are generated so that the signal level rises twice. Further, the reference signal generation circuit 34 increases or decreases the frequency division ratio used for generation of the I arm I and Q arm Q by the control signal S6 output from the control circuit 39.

  The exclusive OR circuit (EXOR) 35 is a phase comparison circuit that compares the phases of the I arm I and the binarized signal S4 (FIG. 5C), and exclusively uses the I arm I and the binarized signal S4. Outputs the phase comparison result based on the logical sum signal. The exclusive OR circuit (EXOR) 36 is a phase comparison circuit that compares the phase of the Q arm Q and the binarized signal S4, and compares the phase of the Q arm Q and the binarized signal S4 using an exclusive OR signal. Output the result.

  Sampling circuits (SH) 37 and 38 sample the phase comparison results output from the exclusive OR circuits 35 and 36, respectively, with the sampling signal SP1 and output the results (FIGS. 5E and 5F). Thus, in this embodiment, the PLL circuit 33 obtains the phase comparison result for the I arm I and the Q arm Q twice in each phase. As a result, the PLL circuit 33 performs four times in a half cycle of the I arm I. Get the phase comparison result.

  The control circuit 39 outputs the control signal S6 to the reference signal generation circuit 34 based on the phase comparison results EXI and EXQ thus obtained from the sampling circuits 37 and 38 in this way, whereby the I arm I is the input signal 2. The phase is synchronized with the value signal S4.

  That is, the control circuit 39 totals the phase comparison results output from the sampling circuits 37 and 38 in the preamble and the sync in the 1/2 cycle of the I arm, and calculates the total value. Here, in this embodiment, total values ΣEXI and ΣEXQ based on the sum of the phase comparison results are applied to the total value.

  Accordingly, as shown in FIG. 6 in comparison with FIG. 13, the total value ΣEXI relating to the I arm I becomes 0 when the I arm I is phase-synchronized with the binarized signal S4 which is the input signal. When the I-arm I is 180 degrees out of phase with respect to the value signal S4, the value becomes 4, and these values vary in the range from the value 4 to the value 0 according to the phase difference with respect to the value signal S4. It will be. The total value ΣEXQ related to the Q arm Q is 2 when the I arm I is phase-synchronized with the binarized signal S4 and when the I arm I is 180 degrees out of phase with the binarized signal S4. When the phase of the I arm I is 90 degrees ahead of the phase of the input signal IN, the value is 0, and when the phase of the I arm I is 90 degrees behind the phase of the input signal IN, the value is 4.

  Thus, the control circuit 39 determines the total values ΣEXI and ΣEXQ obtained in this way, respectively, and increases or decreases the frequency dividing ratio of the frequency dividing circuit used for generating the reference signals I and Q based on the determination results. 6, the phases of these I arm I and Q arm Q are changed in the direction indicated by the arrows, and the I arm I is phase-synchronized with the input signal IN.

  In this process, the control circuit 39 performs a process so that the convergence speed is faster before the end of the sync than at the end of the sync, at the end of the sync (at time t1 in FIG. 2). Switch.

  That is, in the preamble and the sync before the end of the sync, the control circuit 39 calculates the total value for each phase of the I arm according to the 1/2 cycle of the I arm I by the total of two phases that have gone up in the past from the current phase. ΣEXI and ΣEXQ are calculated. As a result, the control circuit 39 calculates the total values ΣEXI and ΣEXQ for each phase based on the ½ period of the I arm I. When the total values ΣEXI and ΣEXQ are each 2, the control values for the arms I and Q are set to a value of 0. When the total values ΣEXI and ΣEXQ are respectively greater than the value 2, the arms I and Q are Set the control value to value 2. When the total values ΣEXI and ΣEXQ are smaller than 2, respectively, the control values related to the arms I and Q are set to 1.

  The control circuit 39 varies the frequency division ratio of the reference signal generation circuit 34 in the subsequent phase as shown in FIG. 7 by the calculation processing of the control amounts of the I arm I and the Q arm Q set as described above. That is, when the control amount of the Q arm Q is a value of 0, the division ratio used for generating the I arm I and the Q arm Q is set to a value 16 that is a reference division ratio, and the I arm I and the Q arm Q The phase is not changed (indicated by a control amount 0 in FIG. 7). When the control amount of the I arm I is 1, the frequency division ratio of the reference signal generation circuit 34 is increased or decreased from the value 16 by the value 1 according to the control amount of the Q arm Q (in FIG. 7, the increase and decrease are respectively increased and decreased). As a result, the phases of the I arm I and the Q arm Q are changed in a direction in which the I arm I is synchronized with a phase difference of 0 degree. On the contrary, when the control amount of the I arm I is 2, the frequency division ratio of the reference signal generation circuit 34 is increased or decreased from the value 16 by the value 1 according to the control amount of the Q arm Q. The phases of the I arm I and the Q arm Q are changed in a direction in which the I arm I is synchronized by a phase difference of 180 degrees.

  On the other hand, in FIG. 6, as indicated by the symbol A, when the control amount of the I arm I is a value 1 or value 2 and the control amount of the Q arm Q is a value 0, A frequency division ratio is set so as to maintain the state (indicated by symbol X in FIG. 7). Thus, the control circuit 39 prevents a phase synchronization delay due to frequent switching of the control direction.

  That is, when the control amount of the I arm I is 1 or 2 and the control amount of the Q arm Q is 0, the Q arm Q is in phase synchronization with the binarized signal S4. In this case, it is difficult to determine in which direction the division ratio may be controlled depending on the total values ΣEXI and ΣEXQ. In this case, if the control amount is set to a value of 0 as described above with reference to FIG. 14, it becomes difficult to control the phase of the I arm I, which requires time for phase synchronization. In this case, if the control amount is forcibly set so that the phase difference changes in any direction, the frequency of the binarized signal S4 is greatly deviated and the duty ratio is deviated from 50%. In the preamble, as shown by the symbol B in FIG. 8, there is a case where the control direction is frequently switched in the preamble, which requires time for phase synchronization. In the preamble of 3 bytes, It becomes difficult to detect the sink correctly.

  Accordingly, in this embodiment, as shown by an arrow C in FIG. 9 in comparison with FIG. 8, in the preamble, the reference signal generation circuit 34 is controlled in the same manner as the control of the reference signal generation circuit 34 in the immediately preceding cycle. Thus, the control amount is set so that the time required for locking is shortened.

  As a result, the control circuit 39 performs the logical operation of the control amounts of the I arm I and the Q arm Q, and the control amount of the I arm I is 1 or 2, and the control amount of the Q arm Q is 0. In this case, a determination signal S8 (FIG. 9D) in which the signal level rises is generated. Further, the sync start time is detected, and in the preamble until the sync start time, the same control as in the immediately preceding cycle is executed by the rising edge of the determination signal S8.

  Therefore, in the preamble and the sync, the control circuit 39 executes the phase control process based on the sum of the phase comparison results of the ½ cycle for each phase, thereby 4 bits for one bit of the binary signal S4. The frequency division ratio of the counter 34 is varied at the rate of the rotation, and thereby the I arm I is phase-synchronized with the binarized signal S4 at a high speed.

  In this way, the PLL circuit 33 synchronizes the I arm I with the binarized signal S4 in this way, and sequentially performs the latch circuit 40 at the timing of one edge of the Q arm Q that is 90 degrees out of phase with the I arm I. By latching the binarized signal S4, a series of data D1 in the format described above with reference to FIG. 2 is demodulated and output from the binarized signal S4. The PLL circuit 33 detects the start and end of the sync by monitoring this demodulated data D1 by the sync detection circuit 42 described later, and switches the control of the reference signal generation circuit 34 by detecting the start and end of these syncs. As a result, the latch circuit 40 constitutes a demodulation circuit that demodulates the data D1 from the binary signal S4 that is a binary signal. In this case, if the binarized signal S4 is sequentially latched at the timing of the both edges of the Q arm Q, the duty of the binarized signal S4 can be simply corrected.

  That is, when the end of the sync is detected, the control circuit 39 acquires the phase comparison results detected for each of the I arm I and Q arm Q from the sampling circuits 37 and 38 in each phase.

  In addition, the control circuit 39 sets the calculation period of the total values ΣEXI and ΣEXQ to ½ period of the I arm I.

  As a result, when the total values ΣEXI and ΣEXQ are 2, respectively, the control circuit 39 sets the control values related to the arms I and Q to the value 0, and the total values ΣEXI and ΣEXQ are the values, respectively. In the case of 4, the control value for each arm I and Q is set to a value of 2. Further, when the total values ΣEXI and ΣEXQ are each 0, the control values related to the arms I and Q are set to the value 1. Further, based on the control values relating to these arms I and Q, the control amount is calculated by the same arithmetic processing as before the sync end time described above with reference to FIG. The control circuit 39 sets the control amount to the value 0 when the control amount of the I arm I described above for the preamble and the sync is the value 1 or the value 2 and the control amount of the Q arm Q is the value 0. Thus, the frequency division ratio is maintained at the reference frequency division ratio.

  The control circuit 39 sequentially divides the I-arm I by one continuous cycle, statistically processes the control amount calculated for the ½ cycle of the I-arm in this way for each segment, and finally performs the final processing for each cycle. The optimal control amount. Here, in this embodiment, majority vote is applied to this statistical processing. Note that by taking the majority vote in this way, there are rare cases where two types of control amounts with the same number of votes are detected. Thereby, in this case, the control circuit 39 forcibly sets the control amount to zero.

  As a result, the control circuit 39 calculates the control amount in units of 1 bit of the binarized signal S4, and the reference signal generation circuit for three phases among the 4 phases related to the subsequent 1 bit based on the calculated control amount. The frequency division ratio of 34 is held at a value 16, which is the reference frequency division ratio, and the frequency division ratio of the reference signal generation circuit 34 is changed from the value 16 for the remaining one phase, whereby I arm I and Q arm Control the phase of Q.

  When the baud rate setting BAUDR is instructed to perform data processing at 424 [kbps], the PLL circuit 33 sets the frequency dividing ratio used for generating the I arm I, Q arm Q, sampling signal SP1, and the like in the reference signal generation circuit 34 described above. The operation is speeded up so as to correspond to the data transfer rate by reducing it to 1/2.

  Further, when data is processed at the data transfer rate 424 [kbps] in this way, the PLL circuit 33 processes after the end of the sync in the same manner as when data is processed at 212 [kbps]. On the other hand, in the preamble and the sync before the end of the sync, instead of the control amount calculated in one phase of the I arm described above, the control amount is calculated in two phases of the I arm I. The reference signal generation circuit 34 is controlled every two phases according to the amount. Specifically, in this case, the control circuit 39 holds the division ratio of the reference signal generation circuit at the reference division ratio value 8 for one of the two consecutive phases, and the remaining one phase. With respect to, the frequency division ratio is varied by a value of 1 from this reference frequency division ratio in accordance with the control amount, thereby controlling the phases of the I arm I and the Q arm Q.

  The timing adjustment circuit 41 instructs various timings related to switching of these processes in the control circuit 39.

  The sync detection circuit 42 detects a sync from the output data D1 of the PLL circuit 33. Therefore, the processing described later related to the buffer memory 44 and the switching of the operation described above for the PLL circuit 33 are executed based on the detection result by the sync detection circuit 42.

  The shift register 43 operates by a clock (in this case, an I arm) regenerated by the PLL circuit 33, and sequentially receives, transfers and accumulates the received data D1 demodulated by the PLL circuit 33, and stores 1 byte. Is stored, the data stored in the subsequent buffer memory 44 is output. As a result, the shift register 43 performs serial-parallel conversion processing on the output data D1 of the PLL circuit 33 and outputs it. The buffer memory 44 sequentially accumulates the output data of the shift register 43 with the clock reproduced by the PLL circuit 33, and accumulates this with the original clock generated by dividing the carrier signal S2 by the clock generation reset circuit 31. Data is read and output to the shift register 45. Thus, the buffer memory 44 outputs data synchronized with the clock of the binarized signal S4 demodulated by the PLL circuit 33 in synchronization with the clock of the reader / writer 12. The shift register 45 sequentially outputs the data input from the buffer memory 44 one bit at a time, and thereby outputs the data input from the buffer memory 44 through parallel-serial conversion processing.

  The selector 46 switches the operation according to the data output mode switching CLKOEN set in the terminal setting register 32, and selectively selects the output data D1 of the shift register 45 and the input data (binarized signal) S4 of the PLL circuit 33. Output. When the output data D1 of the shift register 45 is selected and output, the encoder 48 converts the output data of the selector 46 into a binary signal by Manchester code using the corresponding clock, and outputs it. Thus, the data processing circuit 22 selectively outputs the binarized signal re-synchronized with the clock of the reader / writer 12 or the received binarized signal S4 according to the setting by the data processing circuit 20. In this case, the process of converting to Manchester code may be omitted, and the output data of the shift register 45 may be output as serial data. Further, the parallel serial conversion process may be omitted and output in units of bytes. It may be.

  Thus, when the data processing circuit 22 selectively outputs the input data S4 of the PLL circuit 33 in this way, the data processing circuit 22 also outputs the clock CK regenerated by the PLL circuit 33.

  As a result, the data processing circuit 22 can selectively output a received binarized signal and a binarized signal with a corrected clock frequency and duty ratio in accordance with the subsequent data processing circuit. In addition, when outputting a binarized signal that has just been received in this way, a clock synchronized with the binarized signal is also output so that the binarized signal can be processed. Is done. As shown in FIG. 10, the clock CK (CLKO) output in this manner can be demodulated by latching the output signal CDRIO by Manchester code at the edge timing of the clock CK and demodulating the binary signal CDRIO. Depending on the phase, either I arm I or Q arm Q is selectively applied.

  In this way, the buffer memory 44 outputs the binarized signal by synchronizing again through the buffer memory 44, and specifically, the buffer memory 44 is a six-stage FIFO (First In First Out) 44A to 44F that sequentially transfers data. It is formed by.

  That is, as described above with reference to FIG. 2, in the data applied to this system, a length LEN indicating the amount of payload data is arranged following the sync, and when this length LEN is a value FF, a maximum of 257 bytes is arranged. Data is assigned to the payload. On the other hand, when a clock is generated using a ceramic oscillator, the frequency of the carrier signal varies in a frequency range of 13.41 to 13.71 [MHz].

  Thus, when transmitting 257 bytes of payload data at a data transfer rate of 212 kbps or 424 kbps, the time required for transmission varies within a range of 6 bytes or less in terms of the amount of data to be transmitted. Become.

  As a result, when the buffer memory 44 accumulates the output data from the PLL circuit 33 for 3 bytes, the output of this data is started. With this, the output data from the PLL circuit 33 is reduced by the minimum memory capacity. The signal is output in synchronization with the clock on the reader / writer 12 side.

  More specifically, as shown in FIG. 11, the buffer memory 44 converts the 4-byte data of the preamble 2 bytes (00, 00) and the sync (b2, 4d) into FIFOs from the input stage side to the fourth stage, respectively. The data demodulated by the PLL circuit 33 is sequentially input to the shift register 43 while being held in the data order. Each time the shift register 43 sequentially transfers the output data of the PLL circuit 33 and transfers 1 bit, the sync detection circuit 42 detects whether or not the held 8-bit data matches the first 1 byte of the sync. As a result, the sync detection circuit 42 detects the start of sync.

  When the start of the sync is detected in this way, the shift register 43 similarly transfers the sequentially input data, and the sync detection circuit 42 detects whether or not the subsequent 1 byte matches the sync. Thus, the end of the sync is detected.

  When the end of sync is detected in this way, the buffer memory 44 sequentially transfers the held data to the FIFO of the final stage, and the first byte data (00) related to the preamble is transferred to the shift register 45 on the output side. At the same time, the remaining 3 bytes of data set at the beginning are stored in the FIFO from the output stage side FIFO to the third stage. As a result, the buffer memory 44 secures an empty area for 3 bytes on the input side.

  Further, the buffer memory 44 outputs the data stored sequentially via the shift register 45, and sequentially inputs the length LEN and payload data input following the sync via the shift register 43 in units of bytes. And store in free space. Thereby, even if the clock of the mobile phone 14 to be communicated is shifted to the higher frequency side, the buffer memory 44 secures a free space of 3 bytes and sequentially inputs data. Can be replaced. In addition, even when the clock of the mobile phone 14 to be communicated is shifted to the lower frequency side, the clock of the data that is sequentially input by first holding the 3-byte data by the first set data Can be replaced.

(2) Operation of Embodiment In the above configuration, in this IC card system 11 (FIG. 1), when processing of electronic money or the like is executed by the passive type, control of the data processing circuit 20 in the reader / writer 12 is performed. When the carrier signal S2 generated by the crystal resonator is transmitted from the antenna 25 and the IC card 13 and the mobile phone 14 are brought close to the reader / writer, the carrier is transferred to the antenna of the IC card 13 and the antenna of the IC card unit 17 of the mobile phone 14. A signal is induced. In this IC card system 11, an operating power supply is generated in the IC card 13 and the IC card unit 17 of the mobile phone 14 by the induced carrier signal, and the IC card 13 and the IC card unit 17 of the mobile phone 14 are generated by this power supply. Start operation.

  In this state, in the IC card system 11, the data processing circuit 20 of the reader / writer 12 generates a transmission data signal S3 based on Manchester code based on, for example, command data related to the call, and the RF transmission / reception circuit 21 transmits the transmission data signal S3. Thus, the carrier signal S2 transmitted from the antenna 25 is amplitude-modulated, whereby data such as this command is transmitted from the antenna 25.

  In the IC card 13 and the IC card unit 17 of the mobile phone 14, after the amplitude modulation signal by the amplitude modulation is received by the antenna, it is detected and binarized by the envelope detection, and the transmission data generated by the reader / writer 12. The signal (binarized signal) is demodulated. Further, the clock is regenerated from the transmission data signal (binarized signal), and the data transmitted from the reader / writer 12 is regenerated by processing the binarized signal by this clock. When a response or the like is returned to the reader / writer 12 by the reproduced data, a clock is generated by dividing the carrier signal induced in the antenna, and transmission data based on Manchester code is transmitted using the data provided for transmission by this clock. A signal is generated, and the terminal impedance of the antenna is switched by the transmission data signal.

  As a result, on the reader / writer 12 side, the signal level of the carrier signal S2 related to the terminal voltage of the antenna 25 changes in response to the switching of the termination impedance on the transmission side. 13. Data transmitted from the mobile phone 14 is received.

  In the reader / writer 12, the amplitude modulation signal is detected by the RF circuit 21 and binarized, and the transmission data signal generated on the transmission side is reproduced by the binarized signal S4. Also, after the duty ratio and frequency of the binarized signal S4 are corrected by the data processing circuit 22, the data processing circuit 20 regenerates the clock, and the binarized signal is processed by this clock, and the IC card 13, Data sent from the mobile phone 14 is reproduced.

  As a result, in the IC card system 11, various data can be transmitted and received between the reader / writer 12, the IC card 13, and the mobile phone 14 to execute a series of processes related to processing such as electronic money.

  On the other hand, when the reader / writer 12 is activated from the IC card unit 17 of the mobile phone 14 by the active type, the transmission of the carrier signal S2 from the reader / writer 12 is stopped and the mobile phone 14 In the IC card unit 17, a carrier signal generated by the ceramic vibrator is divided to generate a clock, and a binary signal of data to be transmitted is generated by this clock. The carrier signal is amplitude-modulated by this binarized signal and transmitted from the antenna. Thus, in this case, when the mobile phone 14 is brought close to the reader / writer 12, this amplitude modulation signal is induced in the antenna 25 of the reader / writer 12, and this amplitude modulation signal is detected by the RF circuit 21 and binarized. The transmission data signal generated on the transmission side is reproduced by the binary signal S4. Also, after the duty ratio and frequency of the binarized signal S4 are corrected by the data processing circuit 22, the data processing circuit 20 regenerates the clock, and the binarized signal is processed by this clock, and the IC card 13, Data sent from the mobile phone 14 is reproduced.

  Thus, in the case of the passive type, in the binarized signal S4 detected on the reader / writer 12 side, a highly accurate carrier signal S2 generated by the reader / writer 12 using a crystal resonator is divided by a clock. Thus, even when data is directly input to the data processing circuit 20 to reproduce data, the data can be reproduced simply and reliably by reproducing the clock.

  However, when receiving data from the IC card unit 17 of the active type, the binarized signal S4 is generated by the clock obtained by dividing the carrier signal having a large frequency deviation generated by the ceramic vibrator in the mobile phone 14. When the binarized signal S4 is directly input to the data processing circuit 20 to reproduce the data, it may be difficult for the PLL circuit of the data processing circuit 20 to reproduce the clock. In some cases, it is difficult to reproduce correctly.

  In particular, in this IC card system 11, the duty ratio of the binarized signal S4 received on the reader / writer 12 side changes due to a change in the distance between the reader / writer 12 and the mobile phone 14, and the clock frequency is changed. If the duty ratio changes in this manner in a dispersed state, it becomes difficult to correctly reproduce the data.

  As a result, in this IC card system 11, the duty ratio and frequency of the binarized signal S4 detected by the RF transmission / reception circuit 21 are corrected by the data processing circuit 22 and input to the data processing circuit 20, whereby the clock frequency varies. Even when the duty ratio changes from 50 [%] in this state, the data can be correctly reproduced.

  Thus, the binarized signal S4 received by the passive type operation and the active type operation in this way (FIG. 3) is processed by the data processing circuit 22 with its clock recovered by the PLL circuit 22. That is, in the PLL circuit 22 (FIG. 4), the carrier signal S2 generated on the reader / writer 12 side is frequency-divided by the reference signal generation circuit 34 to generate the I arm I and Q arm Q having a phase difference of 90 degrees. The value signal S4 is phase-compared with the I arm I and the Q arm Q by the exclusive OR circuits 35 and 36 constituting the phase comparison circuit, respectively. Further, the phase comparison result by this phase comparison is input to the control circuit 39 via the sampling circuits 37 and 38, and the I arm is converted into the binary signal S4 by the control of the reference signal generation circuit 34 of the control circuit 39 by this phase comparison result. The frequency division ratio used for generating the I arm I and the Q arm Q is varied so as to be phase-synchronized with each other. In the control of the reference signal generation circuit 34, in this embodiment, the frequency division ratios related to the I arm I and the Q arm Q are varied by a constant period, and this constant period is determined by the preamble and the sync (FIG. 2). While the ratio is set to four times for one cycle of the I arm I, it is set to a ratio of one time for one cycle of the I arm I after the length LEN.

  As a result, in this embodiment, in the preamble of the binarized signal S4 that is a binarized signal, the constant cycle related to the control of the reference signal generation circuit 34 is set to a shorter cycle than the payload portion. Therefore, in the preamble, a reference signal is generated by this preamble because a pattern is provided to synchronize the PLL circuit, and the signal level is switched in synchronization with the clock, which is suitable for synchronization. If the fixed period related to the control of the circuit 34 is set to a short period, the I arm can be changed to the binarized signal S4 in a short time even when the clock frequency related to the binarized signal S4 is deviated. The phase can be synchronized.

  On the other hand, after the synchronization is established by the preamble as described above, when the operation is performed by the passive type, the frequency dividing ratio used for generating the I arm I and the Q arm Q is set to a certain reference frequency dividing ratio. By maintaining, established synchronization can be maintained. However, when operating by the active type, the frequency of the clock generated on the mobile phone 14 side is deviated, so if it is maintained at a constant frequency division ratio in this way, the synchronization gradually shifts and finally Is out of sync.

  However, in the payload portion, the change pattern of the signal level changes variously according to the data to be transmitted, and if the frequency division ratio is controlled in the same manner as in the preamble, synchronization is easily lost. However, in this embodiment, since the control of the frequency division ratio is set to a period longer than that of the preamble portion, more specifically, the ratio is set to once per bit, thereby preventing loss of synchronization. On the other hand, the I-arm I can be held in synchronization with the binarized signal S4 so as to correct the frequency deviation in the clock of the binarized signal S4. However, the data can be reproduced by reliably reproducing the clock.

  However, in the preamble, when the Q arm Q is phase-synchronized with the binarized signal S4 (FIG. 6), it is difficult to determine in which direction the division ratio should be changed depending on the phase comparison result. . In this case, if the reference frequency division ratio is maintained without any control, a pattern in which the signal level is switched at a constant period is assigned to the preamble. It takes time, which prevents synchronization from being established in the preamble.

  In addition, if the frequency division ratio is forcibly changed in one direction, in this case, when the duty ratio is deviated from 50 [%], the control direction may be frequently switched. It takes time, and it becomes difficult to correctly detect the sync, making it difficult to reproduce data (FIG. 8).

  For this reason, in this embodiment, the control circuit 39 detects that the Q arm Q is in phase synchronization with the binarized signal S4. In this case, the control is the same as the control of the reference signal generation circuit 34 in the immediately preceding cycle. Then, the reference signal generation circuit 34 is controlled (FIG. 9).

  As a result, in this embodiment, the state where the Q arm Q is phase-synchronized with the binarized signal S4 in the direction in which the I arm I is phase-synchronized with the binarized signal S4 can be eliminated in a short time. Therefore, the time required for the phase synchronization of the I arm I can be shortened as compared with the conventional case. Thus, in this embodiment, even when the duty ratio changes from 50 [%] with the clock frequency varying, it is possible to correctly reproduce the data.

  In this embodiment, such a phase comparison result is sampled by the sampling circuits 37 and 38 and input to the control circuit 39 (FIG. 5), and for each of the I arm I and the Q arm Q, in half the period of the I arm. After the sampling results are summed, the total value is determined and the control amount of each arm is calculated.

  Further, in the control as described above, in the preamble, the total control amount is calculated by the calculation processing of the control amount of each arm, and the frequency division ratio of the reference signal generation circuit 34 related to the subsequent phase is set. In the preamble, a series of processes relating to the control of the frequency division ratio is repeated for each phase, and the reference signal generation circuit 34 is controlled for each phase.

  In this embodiment, the number of samplings in the sampling circuits 37 and 38 is set to 2 per phase, and the total value is calculated. Thereby, in this embodiment, the phase shift between the I arm I and the Q arm Q can be detected with higher resolution than in the prior art. Accordingly, even if the I arm I is slightly out of phase with the binarized signal S4, the phases of the I arm I and the Q arm Q are adjusted so that the I arm I is phase-synchronized with the binarized signal S4. Can be controlled. Accordingly, the I arm I can be phase-synchronized with the binarized signal S4 with high accuracy, and it is difficult to lose synchronization in the subsequent payload, and this is applied when the clock frequency is deviated. Thus, the data can be reproduced correctly.

  On the other hand, after the sync is completed, similarly, the total value is calculated by the 1/2 cycle of the I arm, and this total value is determined in the same manner as before the sync ends, and the control related to each arm is performed. The amount is calculated, and a total control amount is obtained. In this case, the total control amount is totaled for each cycle of the I arm, and the final control amount is calculated, and this final control amount constitutes this one cycle for each cycle of the I arm. The division ratio in one phase is controlled by the reference division ratio, and the phase of the I arm I is controlled so that the phase synchronization is not lost. Accordingly, in this case, the I arm I and the Q arm Q are phase-controlled at a rate of once per 1 bit of the binarized signal S4 so that the phase synchronization is not lost.

  In this embodiment, the I-arm is thus synchronized with the binarized signal S4, and the binarized signal S4 is latched by the latch circuit 40 by the Q-arm that is 90 degrees out of phase with the I-arm. Thus, the binary signal S4 by Manchester code is demodulated.

  On the other hand, the binarized signal S4 is processed in such a manner as described above, and the data processing circuit 22 controls the data processing circuit 20 to change the data transfer rate from 212 [kbps] to 424 [kbps]. ].

  In this case, in the data processing circuit 22, as in the case where the data transfer rate is 212 [kbps], the phase control of the I arm I and the Q arm Q causes the duty ratio of the binarized signal S4 to be 50 [%]. It was found that the data could not be played back correctly when changed from.

  Therefore, in this embodiment, when the data transfer rate is 424 [kbps], the phase control of the I arm I and the Q arm Q at a rate of once per phase of the binarized signal S4 before the sync is 2 phases. Can be switched to once. As a result, in this embodiment, when the binarized signal is processed by switching the frequency of the I arm and the Q arm to a high frequency, compared to the case where the frequency of the I arm and the Q arm is low, The operation is switched so that the control cycle becomes longer, and the setting is made so that data can be reliably reproduced.

  In the data processing circuit 22, the data demodulated by the PLL circuit 33 is serial-parallel converted by the shift register 43, stored in the buffer memory 44, read out from the buffer memory 44, and then shifted by the shift register 45. Parallel-serial conversion processing is performed, and the signal is converted into a binary signal by the original Manchester code and output. In the writing and reading processing in the buffer memory 44, the output data D1 of the PLL circuit 33 is output by replacing the clock of the binarized signal S4 with the clock of the reader / writer 12.

  As a result, the binarized signal input to the data processing circuit 20 has the duty ratio of 50 [%] and the reader / writer 12 even when the duty ratio changes from 50 [%] while the clock frequency varies. Thus, the data can be reproduced and processed correctly also by the data processing circuit 20 which is output in synchronization with the clock of the data, and is premised on the passive operation.

  When outputting the binarized signal in this manner, the data processing circuit 22 can also directly output the input signal S4 of the PLL circuit 33 by setting from the outside. In this case, the input signal S1 is supplied to the input signal S1. Synchronized clocks can also be output together. This makes it possible to switch the output form of the processing results in various ways according to the external device and widely apply it to various systems.

(3) Advantages of the embodiment According to the above configuration, the phase of the I arm and the Q arm, which are reference signals different in phase by 90 degrees, is controlled by the phase comparison result with the input signal, and one of these reference signals is input. When the phase comparison result that the other reference signal is phase-synchronized with the input signal is obtained by synchronizing the phase with the signal, by continuing the immediately preceding control, the clock frequency varies, Even when the duty ratio changes from 50 [%], data can be correctly reproduced.

  Further, by dividing the carrier signal to generate the I arm and the Q arm, the division ratio is controlled, and the phases of the I arm and the Q arm are controlled. The phase of the arm can be controlled.

  In addition, at the end of the sync following the preamble, the control cycle is switched, and in the preamble, the control cycle is set to be shorter than that of the payload portion. By effectively using the format, the control cycle can be reliably switched between the preamble and the payload.

  Further, the data is demodulated by latching the binarized signal by one of the clocks of the I-arm and the Q-arm thus phase-synchronized, so that the duty ratio is 50 [%] in a state where the clock frequency varies. Data can be reproduced correctly even if the change occurs.

  In addition, the reproduced data is sequentially recorded by the buffer memory 44, and the recorded data is read out by another clock and output, so that the data by the frequency-shifted clock is output by the clock of the reader / writer. The reproduced data can be processed by the data processing circuit 20 which is a processing circuit based on the clock of the reader / writer.

  Further, by modulating and outputting the output data of this buffer memory, the duty ratio and frequency of the received binarized signal can be corrected and output so as to be processed by the same type of data processing circuit.

  When the input data of the PLL circuit and the output data of the buffer memory are selectively output by the selector and the input data of the buffer memory is selectively output, the binarized signal is output by outputting the corresponding clock together. Depending on the external circuit involved in this process, the output form of the process result can be selected in various ways.

  In addition, for each of the four phases dividing one cycle of the I arm by the I arm and the Q arm, the phase comparison result related to the I arm and the phase comparison result related to the Q arm are sampled, and the phase comparison result related to the I arm and the Q arm By acquiring the phase comparison result according to the above in the control circuit, for example, the number of times of sampling in one phase can be set to a plurality of times, and the phase synchronization detection accuracy can be improved.

  In the above-described embodiment, the case where the phase comparison result is sampled and processed twice in one phase has been described. However, the present invention is not limited to this, and the phase comparison result is obtained three or more times. In the case of sampling and processing, the number of samplings can be variously set as required, such as when processing by one sampling.

  In the above embodiment, when the data transfer rate is 212 [kbps], the phase of the I arm and the Q arm is once per phase until the end of the sync and once per bit after the sync. When the data transfer rate is 424 [kbps], the phase of the I arm and Q arm is controlled once every two phases until the end of the sync and once per bit after the sync. However, the present invention is not limited to this, and the period related to these controls can be variously set as necessary without departing from the spirit of the present invention.

  In the above-described embodiment, the case where the frequency and duty ratio of the binarized signal are corrected and processed by the subsequent data processing circuit has been described. However, the present invention is not limited to this, and the present invention is not limited to this. You may make it apply invention. In this way, the above-described data processing circuit 22 can be omitted, and the subsequent data processing circuit can be used as both a passive type and an active type.

  In the above-described embodiments, the case where the present invention is applied to an IC card system has been described. However, the present invention is not limited to this and can be widely applied to a wireless communication system in which the duty ratio changes variously.

  The present invention relates to an integrated circuit, a reproducing apparatus, and a reproducing method, and can be applied to, for example, a non-contact type IC card system.

It is a block diagram which shows the IC card system which concerns on Example 1 of this invention. It is a chart which shows the data format in the IC card system of FIG. It is a block diagram which shows the data processing circuit in the IC card system of FIG. FIG. 4 is a block diagram showing a PLL circuit in the data processing circuit of FIG. 3. 6 is a time chart for explaining a phase comparison result in the PLL circuit of FIG. 6 is a chart showing a relationship between a phase comparison result of FIG. 5 and setting of a control amount. It is a graph which shows the relationship between the controlled variable in FIG. 6, and the total controlled variable. It is a time chart which shows operation | movement of a PLL circuit by the relationship with the setting by the diagram of FIG. It is a time chart which shows operation | movement of a PLL circuit by the setting by the diagram of FIG. It is a time chart used for description of the output of a data processing circuit. It is a block diagram with which it uses for description of operation | movement in a buffer memory. It is a time chart with which it uses for description of the phase comparison result in the conventional PLL circuit. 13 is a chart showing a relationship between a phase comparison result of FIG. 12 and a control amount. FIG. 14 is a chart showing control of the PLL circuit by setting according to the chart of FIG. 13. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... IC card system, 12 ... Reader / writer, 13 ... IC card, 14 ... Mobile phone, 17 ... IC card part, 20, 22 ... Data processing circuit, 12 ... RF transmission / reception circuit, 25 ... ... Antenna, 33 ... PLL circuit, 34 ... Reference signal generation circuit, 35, 36 ... Exclusive OR circuit, 37, 38 ... Sampling circuit, 39 ... Control circuit, 43, 45 ... Shift register, 44 …… Buffer memory, 44A to 44F …… FIFO

Claims (10)

In an integrated circuit that regenerates a clock from a binarized signal obtained by binarizing a detection signal of a radio communication wave,
A reference signal generation circuit for generating an I arm and a Q arm, which are reference signals having different phases by 90 degrees;
A phase comparison circuit for the I arm that compares the phase of the I arm and the binarized signal and outputs a phase comparison result for the I arm;
A phase comparison circuit for the Q arm that compares the phase of the Q arm and the binarized signal and outputs a phase comparison result for the Q arm;
The phase of the I arm and the Q arm is changed by the control of the reference signal generation circuit based on the phase comparison result for the I arm and the phase comparison result for the Q arm, and the I arm is changed to the binarized signal. A control circuit for phase synchronization,
Set the I arm or Q arm to the clock,
The control circuit includes:
Controlling the reference signal generation circuit according to a certain period in the I arm;
In the preamble in the binarized signal, the fixed period is shortened compared to the payload portion of the binarized signal,
When phase synchronization of the Q arm to the binarized signal is detected in the preamble based on the phase comparison result for the Q arm, the control is the same as the control of the reference signal generation circuit in the immediately preceding fixed period. An integrated circuit that controls the reference signal generation circuit. The reference signal generation circuit is
A counter that divides a reference signal to generate the I arm and the Q arm;
Control of the reference signal generation circuit is
The integrated circuit according to claim 1, wherein the control is to set a division ratio of the counter. The control circuit includes:
By switching the constant period at the end of the sync following the preamble,
2. The integrated circuit according to claim 1, wherein, in the preamble, the constant period is shorter than a portion of a payload of the binarized signal. The integrated circuit according to claim 1, further comprising: a demodulating circuit that processes the binarized signal by the clock and demodulates data from the binarized signal. 5. A buffer memory that sequentially records the data, and reads out and outputs the recorded data with another clock, thereby replacing the clock of the data with the other clock. 5. An integrated circuit according to 1. The integrated circuit according to claim 5, further comprising an encoder that converts output data of the buffer memory into a binary signal corresponding to the binarized signal. A selector that selects the binarized signal or the data output from the buffer memory;
The integrated circuit according to claim 6, wherein, when at least the selector selects the binarized signal, the clock is output from a clock output terminal to the outside. The control circuit includes:
The phase comparison result related to the I arm and the phase comparison related to the Q arm for each phase formed by switching one signal level in the I arm and the Q arm and dividing one cycle of the I arm into four periods. 2. The accumulation according to claim 1, wherein the phase comparison result relating to the I arm and the phase comparison result relating to the Q arm are obtained by sampling the result a certain number of times and obtaining the sampling result. circuit. In a playback device for playing back data transmitted by wireless communication waves,
An RF circuit that generates a detection signal of the radio communication wave, binarizes the detection signal, and generates a binarized signal;
A reference signal generation circuit for generating an I arm and a Q arm, which are reference signals having different phases by 90 degrees;
A phase comparison circuit for the I arm that compares the phase of the I arm and the binarized signal and outputs a phase comparison result for the I arm;
A phase comparison circuit for the Q arm that compares the phase of the Q arm and the binarized signal and outputs a phase comparison result for the Q arm;
The phase of the I arm and the Q arm is changed by the control of the reference signal generation circuit based on the phase comparison result for the I arm and the phase comparison result for the Q arm, and the I arm is changed to the binarized signal. A control circuit for phase synchronization;
A demodulation circuit that processes the binarized signal by the I arm or the Q arm and reproduces the data;
The control circuit includes:
Controlling the reference signal generation circuit according to a certain period in the I arm;
In the preamble in the binarized signal, the fixed period is shortened compared to the payload portion of the binarized signal,
When phase synchronization of the Q arm to the binarized signal is detected in the preamble based on the phase comparison result for the Q arm, the control is the same as the control of the reference signal generation circuit in the immediately preceding fixed period. And a control apparatus for controlling the reference signal generation circuit. In a reproduction method for reproducing data transmitted by a wireless communication wave,
Generating a detection signal of the wireless communication wave, binarizing the detection signal to generate a binary signal, and generating a binary signal;
A step of generating a reference signal for generating an I arm and a Q arm, which are reference signals having a phase difference of 90 degrees;
A phase comparison step for the I arm that compares the phase of the I arm with the binarized signal and outputs a phase comparison result for the I arm;
A phase comparison step for the Q arm that compares the phase of the Q arm and the binarized signal and outputs a phase comparison result for the Q arm;
The phase of the I arm and the Q arm is changed by the control of the reference signal generation circuit based on the phase comparison result for the I arm and the phase comparison result for the Q arm, and the I arm is changed to the binarized signal. A phase synchronization control step;
A demodulation step of processing the binarized signal by the I arm or Q arm to reproduce the data;
The control step includes
Obtaining a phase comparison result for the I arm and a phase comparison result for the Q arm according to a certain period in the I arm, and controlling the operation of the reference signal generation circuit;
In the preamble in the binarized signal, the fixed period is shortened compared to the payload portion of the binarized signal,
When phase synchronization of the Q arm to the binarized signal is detected in the preamble based on the phase comparison result for the Q arm, the control is the same as the control of the reference signal generation circuit in the immediately preceding fixed period. And controlling the reference signal generation circuit.

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