JPS6389052A - Switching power circuit - Google Patents
Switching power circuitInfo
- Publication number
- JPS6389052A JPS6389052A JP23416286A JP23416286A JPS6389052A JP S6389052 A JPS6389052 A JP S6389052A JP 23416286 A JP23416286 A JP 23416286A JP 23416286 A JP23416286 A JP 23416286A JP S6389052 A JPS6389052 A JP S6389052A
- Authority
- JP
- Japan
- Prior art keywords
- winding
- power supply
- capacitor
- tertiary
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004804 winding Methods 0.000 claims abstract description 70
- 239000003990 capacitor Substances 0.000 claims abstract description 26
- 230000009466 transformation Effects 0.000 claims 1
- 238000007599 discharging Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
本発明はホワードまたはフライバック式のスイッチング
電源回路に係り、特に開閉素子に付加されるスナバ−に
関するものである。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a forward or flyback type switching power supply circuit, and particularly to a snubber added to a switching element.
「従来の技術」
一般に、第９図に示すように、直流電源（１）の両端間
に、主変圧器（２）の１次巻線（３）と開閉素子（４）
の直列回路を結合し、前記主変圧器（２）の２次巻線（
５）に、整流器（６）とが波回路（７）を結合し、出力
端子（８） （！］）に得られた出力電圧を検出増幅回
路（１０）、アイソレータ（１１）を介して前記開閉素
子（４）に加えて時比率を制御するようにしたいわゆる
ホワードまたはフライバック式スイッチング電源回路が
ある。この電源回路において、従来、スイッチング電源
回路のターンオフ時の開閉素子（４）のスパイク電圧お
よびこれに基因する出力電圧のノイズ電圧を低減するた
めに、開閉素子（４）と並列にダイオード（１２）、抵
抗（１３）およびコンデンサ（１４）をもって構成され
るスナバ−装置が多用されていた。"Prior Art" Generally, as shown in Fig. 9, a primary winding (3) of a main transformer (2) and a switching element (4) are connected between both ends of a DC power supply (1).
The series circuit of the main transformer (2) is connected to the secondary winding (
5), the rectifier (6) and the wave circuit (7) are connected, and the output voltage obtained at the output terminal (8) (!) is detected and transmitted through the amplification circuit (10) and the isolator (11). There is a so-called forward or flyback type switching power supply circuit which controls the duty ratio in addition to the switching element (4). In this power supply circuit, conventionally, a diode (12) is connected in parallel with the switching element (4) in order to reduce the spike voltage of the switching element (4) at turn-off of the switching power supply circuit and the noise voltage of the output voltage caused by this. , a snubber device consisting of a resistor (13) and a capacitor (14) was often used.
「発明が解決しようとする問題点」
この第９図のスイッチング電源回路では、開閉素子（４
）のターンオフ時（第１０図のｔ、−ｔ４）には効果的
にソース・ドレン間電圧（ｖ９）のスパイク電圧は抑制
されるが、開閉素子（４）のターンオン時（第１０図の
ｔ１〜ｔｚ）のコンデンサ（１４）の放電は抵抗（１３
）を通じて行われるので、これは損失を構成する。第１
０図（ｂ） （Ｃ）はコンデンサ（１４）の充放電流（
Ｉｃ）と電圧（Ｖｃ）の特性である。またこの放電電流
（Ｉｒ）は開閉素子（４）にも通ずるので第１０図（ａ
）のｔ工〜ｔ２間のように、ソース・ドレン間電圧（Ｖ
ｑ）と電流（Ｉｑ）とは重なりを発生し、これもまた損
失となるという問題があった。ちなみに、ｔ、〜ｔ４間
の電流Ｉｃは開閉素子（４）のドレン・ソース間に有す
るキャパシタンスへの充電電流であって損失を形成しな
い。"Problems to be Solved by the Invention" In the switching power supply circuit shown in Fig. 9, the switching elements (4
) is turned off (t, -t4 in Figure 10), the spike voltage of the source-drain voltage (v9) is effectively suppressed, but when the switching element (4) is turned on (t1 in Figure 10) ~tz) The discharge of the capacitor (14) is caused by the resistance (13
), this constitutes a loss. 1st
Figure 0 (b) (C) shows the charging and discharging current of the capacitor (14) (
Ic) and voltage (Vc) characteristics. This discharge current (Ir) also passes through the switching element (4), so it is shown in Fig. 10 (a).
), the source-drain voltage (V
There is a problem in that the current (Iq) and the current (Iq) overlap, which also results in loss. Incidentally, the current Ic between t and t4 is a charging current to the capacitance between the drain and source of the switching element (4), and does not cause any loss.
［問題点を解決するための手段」
本発明は以上２つの損失を略零に近く低減しようとする
もので、電源側に主変圧器の］次巻線と開閉素子とを直
列に結合し、前記主変圧器の２次巻線に整流器とろ波回
路を設け、得られた出力電圧を検出増幅して前記開閉素
子の時比率を制御するようにしたスイッチング電源回路
において、前記主変圧時の１次巻線と略同一巻回数を有
する３次巻線を設け、この３次巻線の巻始め側を１次巻
線の巻始め側に結合し、３次巻線の巻終り側と電源側の
正または負の一端との間にコンデンサを結合し、これら
３次巻線とコンデンサとの接合点と。[Means for Solving the Problems] The present invention aims to reduce the above two losses to almost zero, by connecting the secondary winding of the main transformer and the switching element in series on the power supply side, In the switching power supply circuit, a rectifier and a filter circuit are provided in the secondary winding of the main transformer, and the obtained output voltage is detected and amplified to control the duty ratio of the switching element. A tertiary winding having approximately the same number of turns as the primary winding is provided, the winding start side of this tertiary winding is connected to the winding start side of the primary winding, and the winding end side of the tertiary winding is connected to the power supply side. A capacitor is coupled between the positive or negative end of the tertiary winding and the junction of the capacitor.
１次巻線と開閉素子との結合点との間に整流器を結合し
てなるものである。A rectifier is connected between the connection point between the primary winding and the switching element.
「作用」
開閉素子のターン・オフ時の動作は第９図の従来例と全
く同様である。"Operation" The operation of the switching element when it is turned off is exactly the same as that of the conventional example shown in FIG.
ターン・オン時におけるコンデンサの放電は３次巻線を
通じて行なわわ、コンデンサに蓄積されていたエネルギ
は入力に返還され損失を形成しない。また返還されると
同時に、この′７ｔｉ流は３次巻線から】次巻線、開閉
素子へと流れ、−旦入力に返還されたエネルギが２次巻
線を通じて出力される。Discharging of the capacitor at turn-on takes place through the tertiary winding, and the energy stored in the capacitor is returned to the input and does not form a loss. At the same time as being returned, this '7ti current flows from the tertiary winding to the next winding and the switching element, and the energy that was once returned to the input is outputted through the secondary winding.
「実施例」 以下、本発明の実施例を図面に基づき説明する。"Example" Embodiments of the present invention will be described below based on the drawings.
第９図と同一部分は同一符号とする。The same parts as in FIG. 9 are given the same reference numerals.
第１実施例を示す第１図において、直流電源（１）の両
端に、主変圧器（２）の１次巻線（３）と開閉素子とし
てのＭＯ８型ＦＥ’ｒ（４）との直列回路を結合する。In FIG. 1 showing the first embodiment, a primary winding (3) of a main transformer (2) and an MO8 type FE'r (4) as a switching element are connected in series at both ends of a DC power supply (1). Combine circuits.
また、前記主変圧器（２）の２次巻線（５）には、整流
器（６）、転流器（ｚ３）、コイル（２４）とコンデン
サ（２５）による平滑が波回路（７）を介して出力端子
（８） （９）に結合されている。この出力端子（８）
（！１１）には検出増幅回路（１０）、アイソレータ
（１１）を介して前記Ｆ Ｅ Ｔ （４）のゲートに結
合されている。In addition, the secondary winding (5) of the main transformer (2) is equipped with a smoothing wave circuit (7) consisting of a rectifier (6), a commutator (z3), a coil (24), and a capacitor (25). via the output terminals (8) and (9). This output terminal (8)
(!11) is coupled to the gate of the FET (4) via a detection amplifier circuit (10) and an isolator (11).
以上のように構成されたいわゆるホワードまたはフライ
バック式のスイッチング電源回路において、本発明では
、前記主変圧器（２）に、１次巻線（３）と略同一巻回
数の３次巻線（ｚ２）を設け、この３３次巻線（２２）
の巻始め側を１次巻線（３）の巻始め側に結合し、巻終
り側はコンデンサ（２０）を介して直ｄＬ電源（１）の
負側に結合するとともに逆向きの整流器（２１）を介し
てＦ Ｅ Ｔ （４）のドレンに結合してなるものであ
る。In the so-called forward or flyback type switching power supply circuit configured as described above, in the present invention, the main transformer (2) is provided with a tertiary winding (3) having approximately the same number of turns as the primary winding (3). z2) and this 33rd winding (22)
The winding start side of the primary winding (3) is connected to the winding start side of the primary winding (3), and the winding end side is connected to the negative side of the direct dL power supply (1) via a capacitor (20) and a reverse rectifier (21). ) to the drain of FET (4).
以上のような回路構成においてＦ Ｅ Ｔ （４）のタ
ーンオフ時の動作は第９図の従来例と全く同様である。In the circuit configuration as described above, the operation at turn-off of FET (4) is exactly the same as that of the conventional example shown in FIG.
しかし、ターンオン時の放電は３次巻線（２２）を通じ
て行われ、コンデンサ（２０）の充電時に蓄えられてい
たエネルギはこの時入力に返還され損失を形成しない。However, the discharge at turn-on occurs through the tertiary winding (22), and the energy stored during charging of the capacitor (20) is returned to the input at this time and does not form a loss.
また、返還されると同時にこの時の電流（Ｉｃ）は３次
巻線（２２）−＋１次巻線（３）−＋ＦＥＴ（４）間を
流れる。この１次巻線（：３）に流れることは−旦入力
に返還されたエネルギが１次巻線（３）→２次巻線（５
）を通じて出力されることを意味する。Moreover, at the same time as being returned, the current (Ic) at this time flows between the tertiary winding (22)-+primary winding (3)-+FET (4). What happens is that the energy that is returned to the input flows through the primary winding (3) → the secondary winding (5).
).
そして、３次巻線（２２）と１次巻線（３）内のり−ケ
ージインダクタンスにより、この電流（Ｉｅ）の立」二
りおよびピーク値は第２図（ｃ）のように抑制されるの
で、第２図（ａ）に示した電圧（ｖ９）と電流（Ｉｑ）
のように、それぞれが重なり合うことはなく従って、こ
こでも損失の発生は僅少である。The rise and peak values of this current (Ie) are suppressed by the cage inductance in the tertiary winding (22) and the primary winding (3) as shown in Figure 2 (c). , the voltage (v9) and current (Iq) shown in Fig. 2(a)
As shown in FIG.
第１図において、コンデンサ（２０）の他端は電源（１
）の負側に結合したが、点線で示すように正側に結合し
ても同様の作用効果を有する。In Figure 1, the other end of the capacitor (20) is connected to the power supply (1
) is bonded to the negative side of ), but the same effect can be obtained even if it is bonded to the positive side as shown by the dotted line.
第１実施例では、１個の開閉素子（４）を用した場合を
示したが、第３図および第４図に示すように２個の開閉
素子（４ａ）（４ｂ）を用いたカスケード型のホワード
型であってもよい。すなわち、第３図は第１のＦ Ｅ
Ｔ （４ａ）のドレン・ソース間にコンデンサ（２０ａ
）と整流器（２１ａ）の直列回路を結合し、これらの接
続点と電源（１）の負側との間に第１の３次巻線（２２
ａ）を結合し、また、第２のＦ−Ｅ Ｔ （４ｂ）のド
レン・ソース間にコンデンサ（２０ｂ）と整流器（２１
、ｂ）の直列回路を結合し、これらの接続点と電源（１
）の正側との間に第２の３次巻線（２２ｂ）を結合した
ものである。また、第４図は第１と第２のＦＥＴ （４
ａ） （４ｂ）のドレン・ソース間にそれぞれコンデン
サ（２０ａ） （２０ｂ）と整流器（２１ａ） （２１
ｂ）の直列回路を結合し、これらの接続点間に３次巻線
（２２）を挿入したものである。In the first embodiment, a case was shown in which one switching element (4) was used, but as shown in FIGS. 3 and 4, a cascade type using two switching elements (4a) (4b) It may be of the forward type. That is, FIG. 3 shows the first F E
A capacitor (20a) is connected between the drain and source of T (4a).
) and the rectifier (21a), and connect the first tertiary winding (22a) between these connection points and the negative side of the power supply (1).
a), and also connect a capacitor (20b) and a rectifier (21) between the drain and source of the second FET (4b).
, b), and connect these connection points to the power supply (1
), and a second tertiary winding (22b) is connected between the positive side of the coil and the positive side of the coil. Moreover, FIG. 4 shows the first and second FET (4
a) Connect capacitors (20a) (20b) and rectifiers (21a) (21) between the drain and source of (4b), respectively.
The series circuits of b) are connected and a tertiary winding (22) is inserted between these connection points.
第５図は、本発明の他の実施例を示すもので、この例で
は、第１図の回路構成において３次巻線（２２）とコン
デンサ（２０）との間にインダクタンス（２６）を挿入
したものである。このインダクタンス（２６）の挿入に
より、Ｆ Ｅ Ｔ （４）のターン・オン時に、コンデ
ンサ（２０）の２３次巻線（２２）へ通ずる放電電流Ｉ
ｎ、は第２図（ｂ）の点線で示すように緩やかなものと
なり、これに伴い、ＦＥＴ（４）の通過電流１ｑの立上
りや放電電圧（Ｖｃ）の立下りも（ａ）（ｃ）の点線に
示すように緩やかになり、全体の効率を向上させ、ノイ
ズ抑制に効果的である。FIG. 5 shows another embodiment of the present invention. In this example, an inductance (26) is inserted between the tertiary winding (22) and the capacitor (20) in the circuit configuration of FIG. This is what I did. By inserting this inductance (26), when FET (4) is turned on, the discharge current I flowing to the 23rd winding (22) of the capacitor (20)
n becomes gradual as shown by the dotted line in Fig. 2 (b), and accordingly, the rise of the passing current 1q of FET (4) and the fall of the discharge voltage (Vc) also become (a) (c) As shown by the dotted line, it becomes gentler, improving the overall efficiency and being effective in suppressing noise.
第６図は、本発明の他の実施例を示すもので、この例で
は、２次巻線（５）に、インダクタンスの大きな磁気増
幅器（２７）を挿入したものに本発明を適用したもので
、従来は第７図の実線特性のようにターンオフ時のスパ
イク電圧で苦慮していたが、本発明を適用することによ
り、点線特性のような電流（Ｉｑ’）と電圧（Ｖｑ’）
の特性となり、スパイク電圧は大巾に抑制される。FIG. 6 shows another embodiment of the present invention, in which the present invention is applied to a secondary winding (5) in which a magnetic amplifier (27) with large inductance is inserted. , conventionally, the spike voltage at turn-off as shown in the solid line characteristics in Fig. 7 was a problem, but by applying the present invention, the current (Iq') and voltage (Vq') as shown in the dotted line characteristics can be reduced.
The spike voltage is greatly suppressed.
第８図は、本発明の他の実施例を示すもので、この例で
は、主変圧器（２）の２次巻線をもたず、Ｆ Ｅ Ｔ
（４）のドレン・ソース間から出力を得るいわゆるブー
スター型であり、この回路でも同様の作用効果を得るこ
とができる。なお、コンデンサ（２０）は実線状態だけ
でなく、点線状態に結合してもよい。FIG. 8 shows another embodiment of the invention, in which the main transformer (2) does not have a secondary winding, and the F E T
(4) This is a so-called booster type circuit that obtains an output from between the drain and source, and similar effects can be obtained with this circuit. Note that the capacitor (20) may be coupled not only in the solid line state but also in the dotted line state.
「発明の効果」
以−ヒにより従来の回路で発生した前述の２つの損失は
ほとんど零または極小となる。``Effects of the Invention'' As a result, the two losses described above that occurred in the conventional circuit become almost zero or extremely small.
このことはまたコンデンサの容量を大きくしても損失を
増大するようなことがなく、ターンオフ時の電圧のスパ
イク電圧の抑制をより効果的に行うことを可能とする。This also means that even if the capacitance of the capacitor is increased, the loss does not increase, and it is possible to more effectively suppress the voltage spike at turn-off.
またスイッチング周波数をスナバ回路の損失を顧慮する
ことなく増・大することも可能である。It is also possible to increase the switching frequency without considering the loss of the snubber circuit.
第１図は本発明によるスイッチング電源回路の第１実施
例を示す電気回路図、第２図は第１図の特性図、第３回
、第４図、第５図、第６図、第８図はそれぞれ本発明の
異なる実施例を示す電気回路図、第７図は第６図の回路
の特性図、第９図は従来の回路の特性図、第１０図は第
９図の特性図である。
（１）・・・直流電源、（２）・・・主変圧器、（３）
・・・１次巻線、（４） （４ａ） （４ｂ） ・・・
開閉素子、 （５）−２次巻線、（６） ・・・整流器
、（７）・・・ろ波回路、（８）（９）・・・・・・出
力端子、（１０）・・・検出増幅回路、（１１）・・・
アイソレータ、 （２０）（２０ａ） （２０ｂ） −
Ｄ ンデンサ、 （２１）−・・整流器、（２２）（２
２ａ） （２２ｂ） ・＝ ３次巻線、（２６）−・・
インダクタンス、（２第 １ 図
第 ３ 図
第 ２ 図
第 ８ 図
第 ９ 図
第 １０ 図Fig. 1 is an electric circuit diagram showing a first embodiment of the switching power supply circuit according to the present invention, Fig. 2 is a characteristic diagram of Fig. 1, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 8 The figures are electrical circuit diagrams showing different embodiments of the present invention, Figure 7 is a characteristic diagram of the circuit in Figure 6, Figure 9 is a characteristic diagram of a conventional circuit, and Figure 10 is a characteristic diagram of the circuit in Figure 9. be. (1)...DC power supply, (2)...Main transformer, (3)
...Primary winding, (4) (4a) (4b) ...
Switching element, (5) - Secondary winding, (6) ... Rectifier, (7) ... Filter circuit, (8) (9) ... Output terminal, (10) ...・Detection amplifier circuit, (11)...
Isolator, (20) (20a) (20b) -
D capacitor, (21)--rectifier, (22) (2
2a) (22b) ・= Tertiary winding, (26) −・・
Inductance, (2 Fig. 1 Fig. 3 Fig. 2 Fig. 8 Fig. 9 Fig. 10)
Claims (5)
に結合し、前記主変圧器の２次巻線に整流器とろ波回路
を設け、得られた出力電圧を検出増幅して前記開閉素子
の時比率を制御するようにしたスイッチング電源回路に
おいて、前記主変圧時の１次巻線と略同一巻回数を有す
る３次巻線を設け、この３次巻線の巻始め側を１次巻線
の巻始め側に結合し、３次巻線の巻終り側と電源側の正
または負の一端との間にコンデンサを結合し、これら３
次巻線とコンデンサの接合点と、１次巻線と開閉素子と
の結合点との間に整流器を結合してなることを特徴とす
るスイッチング電源回路。(1) The primary winding of the main transformer and the switching element are coupled in series on the power supply side, a rectifier and a filter circuit are provided in the secondary winding of the main transformer, and the resulting output voltage is detected and amplified. In the switching power supply circuit, a tertiary winding having approximately the same number of turns as the primary winding at the time of main transformation is provided, and a winding start side of the tertiary winding is provided. is coupled to the winding start side of the primary winding, and a capacitor is coupled between the winding end side of the tertiary winding and one positive or negative end of the power supply side, and these three
A switching power supply circuit characterized in that a rectifier is coupled between a junction point between a secondary winding and a capacitor and a junction point between a primary winding and a switching element.
、それぞれの開閉素子毎に３次巻線を具備した特許請求
の範囲第１項記載のスイッチング電源回路。(2) The switching power supply circuit according to claim 1, which is a cascade type power supply using two switching elements, and each switching element is provided with a tertiary winding.
、２個の開閉素子に対し１個の３次巻線を具備した特許
請求の範囲第１項記載のスイッチング電源回路。(3) The switching power supply circuit according to claim 1, which is a cascade type power supply using two switching elements, and includes one tertiary winding for each of the two switching elements.
特許請求の範囲第１項記載のスイッチング電源回路。(4) The switching power supply circuit according to claim 1, wherein an inductance is inserted in series with the tertiary winding.
特許請求の範囲第１項記載のスイッチング電源回路。(5) The switching power supply circuit according to claim 1, which comprises a magnetic amplifier inserted into the secondary winding of the main transformer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61234162A JPH07118916B2 (en) | 1986-10-01 | 1986-10-01 | Switching power supply circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61234162A JPH07118916B2 (en) | 1986-10-01 | 1986-10-01 | Switching power supply circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6389052A true JPS6389052A (en) | 1988-04-20 |
| JPH07118916B2 JPH07118916B2 (en) | 1995-12-18 |
Family
ID=16966630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61234162A Expired - Fee Related JPH07118916B2 (en) | 1986-10-01 | 1986-10-01 | Switching power supply circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07118916B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02237466A (en) * | 1989-03-09 | 1990-09-20 | Fuji Elelctrochem Co Ltd | Switching power source |
| JPH03178570A (en) * | 1989-12-07 | 1991-08-02 | Sanken Electric Co Ltd | Switching power supply |
| JP2012034525A (en) * | 2010-08-02 | 2012-02-16 | Nippon Soken Inc | Switching power supply device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6091863A (en) * | 1983-10-26 | 1985-05-23 | Hitachi Ltd | Switching regulator |
-
1986
- 1986-10-01 JP JP61234162A patent/JPH07118916B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6091863A (en) * | 1983-10-26 | 1985-05-23 | Hitachi Ltd | Switching regulator |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02237466A (en) * | 1989-03-09 | 1990-09-20 | Fuji Elelctrochem Co Ltd | Switching power source |
| JPH03178570A (en) * | 1989-12-07 | 1991-08-02 | Sanken Electric Co Ltd | Switching power supply |
| JP2012034525A (en) * | 2010-08-02 | 2012-02-16 | Nippon Soken Inc | Switching power supply device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07118916B2 (en) | 1995-12-18 |
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|---|---|---|---|
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| LAPS | Cancellation because of no payment of annual fees |