JPS6388525A - Scanning circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit which uses polyphase clock pulses and switches by using individual TFT elements for the rising and falling of a signal, applying polyphase clock pulses to respective gate electrodes, and controlling the timing of rising and falling. CONSTITUTION:This scanning circuit consists of a scanning circuit 2 which consists of a shift register, etc., and generates a scanning voltage, thin-film transistor TFT elements T1 and T3 connected to the output line 3 of the scanning circuit 2, TFT elements T2 and T4 connected to a DC voltage line 6, two-phase clock wiring 4 connected to the gate electrodes of those TFT elements, and output wiring 5. A circuit for obtaining two outputs for outputs phi1, phi2... of the scanning circuit 2 is composed of four TFT elements. Then, the TFT elements T1, T3... are used for a load 7 when the pulses rise and the TFT elements T2 and T4 are used when the pulses fall. Thus, the TFT elements dedicated to the rising and falling are used to obtain a fast waveform. Consequently, even when the pitch of a scanning voltage generating circuit is narrow, the number of output scanning voltages is easily increased.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a drive circuit for a liquid crystal display.

In particular, the present invention relates to a circuit suitable for a drive circuit of an active matrix liquid crystal display using thin film transistors (TPT).

[Conventional technology]

An active matrix display using TFT is a display that can incorporate a driving circuit around the display part, and this peripheral circuit has the potential to make the display device smaller and lower in price.

A circuit is required to drive each of the scanning side wiring (also called horizontal scanning wiring, X direction wiring) and signal side wiring (vertical signal wiring, Y direction wiring) of the display section, but currently, driving LSI etc. Display voltages are applied using FPC connections and chip-on-board technology for mounting chips on display substrates. In order to incorporate these circuits into the display section, polycrystalline silicon (Poly Si), cadmium selenide (CdSe), or a silicon film whose crystallinity has been improved by laser or heat is used as a TFT? It is being researched as a semiconductor film for R atoms. Since TFT elements using these films have high mobility μ, e and large mutual conductance gm, there is a high possibility of forming a circuit that satisfies the operating speed required to drive the display section.

Considering the larger area and higher definition of displays with built-in peripheral drive circuits, it is important to leave as much margin as possible in the processing accuracy of the manufacturing process, and in particular, the larger the minimum line width of the pattern, the better the manufacturing yield. will improve. Also,
In order to increase the operating speed of the circuit, it is necessary to increase the ratio W/L between the channel width W and the channel length of the TFT element, but the channel length is determined by the minimum dimension of processing accuracy. Therefore, it is necessary to design the channel width W to be large. For this reason, when manufacturing peripheral drive circuits, it is necessary to increase the operating speed.

Even when formed on a substrate, a large area is not required, and it is easy to form a scanning circuit with a large number of stages in large-area displays and the like where miniaturization of processing accuracy is difficult.

FIG. 3 shows a modification of the embodiment shown in FIG. 1, and FIG. 4 shows its driving waveform. ... is the three-phase clock voltage ψ1. ψ2
．． Using ψδ, divide the output into three parts and calculate the output as pressure V O1t V
It is configured to output O21V o s.... At this time, the clock applied to T l # T z is ψ1. ψ
A clock shifted by one phase, such as 2, is applied.

Similarly, for TI and T2, ψ2. ψ8, TIl, T6
ψ♂ and ψ1 are applied to. From the embodiments shown in FIGS. 3 and 4, it is easy to further construct 4-phase, 5-phase,...
and the clock is multiphase, and the output of the shift voltage generation circuit is 4
It can also be divided into multiple parts, such as division, five divisions, etc.

FIG. 5 shows an example in which the circuit of the above embodiment is connected in two stages.

In this circuit, the outputs φl, φ2 .・
. . ., a clock with twice the frequency ψ, ψ2, and a clock with four times the frequency ψ8. Using ψ4, the area of 1 circuit increases. When the area of 0 circuit increases and the pitch of the pixels of the display section becomes finer, it becomes difficult to match the pitch of the output wiring of the 1 display section and the output of the circuit section. The nine circuit sections are larger than the display section, and the circuits are formed on both sides of one display section, making panel design difficult.

Furthermore, the problem arises that the area of the entire panel increases due to the circuit portion.

To solve this problem, as described in Japanese Patent Publication No. 56-31790, a circuit has been proposed in which a multiplexer circuit using multi-phase clocks is attached to the output of a single-stage circuit to increase the output by the number of clock phases. . This circuit is a scanning circuit used in an imaging device, and since the driving method is different from that of an active matrix display, the circuit configuration is also different.

[Problem that the invention seeks to solve]

The present invention provides high-speed voltage rise and fall for use in the scanning side circuit of an active matrix display.
An object of the present invention is to provide a circuit that performs switching using multiphase clock pulses.

[Means for solving problems]

This configuration requires separate T for the rising and falling edges of the signal.
This is achieved by using FT elements, applying multiphase clock pulses to the gate electrodes of each TFT element, and controlling the timing of rise and fall.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIG. TFT elements T1 and T8 connected to the output line 3 of the scanning circuit 2, TFT elements T1 and T8 connected to the DC voltage line 6, two-phase clock wiring 4 connected to the gate electrodes of these TFT elements, and output wiring. Consists of 5. Scanning circuit 2 whose waveforms applied to each part are shown in FIG.
Output φ1. φ2. For each of the above, a circuit for obtaining two outputs is formed using four TFT elements.

These TFT elements will be described as n-channel operation.

It goes without saying that the TFT 14 can also operate with a p-channel structure or a combination of n-channel and p-channel structures. φl, φ2. φ1. which has twice the frequency of the output of φ8... A clock of ψ2 is applied to the clock wiring 4. ψ1゜ψ2 are in an inverse relationship to each other. φ1 is at a high level ``1'', ψ1 applied to the gate of T1 is "1", and ψ2 applied to the gate of Tz
is low and when the bell #L II, TI is on, TZ
is turned off, the voltage ψ1 is applied to the load 7 through Tl, and V o 1 becomes II HII. Also, at this time, the Ta(7) gate is in the 'L' state and the Ta(7) gate is in the 'H' state (7), so Ts is off and Ta is on, and the second output Voz is the f4 voltage. line 6
If the level of voltage line 6 is low,
If it is set as ``IJL'', Vow becomes ``IJL''.

Next, in the latter half of the period when φl is in the “HTl” state.

φ1 is "Ln" and ψ2 is "H", and the above state and the on state and off state of the TFT element have a reverse relationship. In this state, V O1 is at the level of the voltage line 6, that is, a L”, VOR is at the level of φ grave, that is, “H
#bawl. In this way, φ1? φ2. Scanning waveform V O1* V o with twice the frequency for φδ...
z + V o s... can be generated.

Here, for the load 7, TFT elements of Tl, Ta, . . . are used when the pulse rises, and TFT elements of TZ and Ta are used when the pulse falls.

That is, since dedicated TFT elements are used for rising and falling edges, it is possible to increase the waveform speed.

In addition, since only two TFT elements are used for the output of one stage, V Of tVozp
Outputs of four scanning voltages Vos and VO4 are obtained. To the embodiment shown in FIG. 5, a circuit for dividing into multiple phases as shown in FIG. 3 is applied, and the first stage is divided into M parts.

If the second stage is divided into N, the output voltage VQI, VO2
..., φ1. φ2. For φδ..., (MXN)
It can be divided into.

FIG. 6 shows TZ and Ta in the embodiment of FIG.

For the gate of each TFT element, ψ2. ψ
8. The configuration in which a clock voltage of ψ1 was applied was changed to φ3. This is a different connection order from ψwork and ψ2. At this time, the capacitance connected to each output temporarily holds the output voltage level, and the output waveform Volt V
O21Voa... can obtain waveforms in which the 11 HH levels partially overlap.

Such a waveform becomes an effective waveform when driving a display using a new method.

As shown in FIG. 6, the circuit configuration of the present invention can be used for changing the connection method to multiphase clock wiring, changing the timing of clock application, and even changing the waveform.

FIG. 7 shows an example in which this embodiment is applied to a display with a built-in peripheral circuit.According to the present invention, the area of the scanning circuit can be reduced to the area where two TFT elements in the output stage can be formed. It becomes possible to form the scanning circuit smaller than the scanning side dimension of the display section 10 within the substrate. As a result, the drive circuit section, which has a high density of TFT elements and a poor manufacturing yield compared to one part per display, can be formed in a small area, and an improvement in the yield during manufacturing of display substrates can be expected.

Further, when performing special processing on only a part of the substrate, for example, a part of the semiconductor is laser annealed.

Alternatively, ion implantation may be performed only on a portion of the 5 circuit section.
In the case of MO3 configuration, etc., the area to be processed can be reduced, and it is expected that one working time can be shortened or variations in characteristics depending on location can be reduced.

FIG. 8 shows a configuration in which the scanning circuit is downsized to provide two systems of identical or similar circuits, so that if a defect occurs in one, the other circuit can be used to repair it.

〔Effect of the invention〕

According to the present invention, it is possible to easily increase the number of scan voltage outputs even when the pitch of the circuit that generates scan voltages is narrow with respect to the pitch of pixels of the display section in a display employing a peripheral drive circuit. effective.

[Brief explanation of the drawing]

Figures 1, 3, 5 and 6 are circuit diagrams showing embodiments of the present invention, Figures 2 and 4 are drive waveform diagrams, Figures 7 and 8 are
The figure is a configuration diagram when the present invention is applied to a display. DESCRIPTION OF SYMBOLS 1...TFT element, 2...Scanning voltage generation circuit, 3...
...Scanning voltage output, 4...Clock wiring, 5...Output, 6...DC voltage wiring.・ , ＼, Agent Patent Attorney Katsuo Ogawa ゝRaku 1 Zuka 2 Figure fV・5 Lai 3 Figure 4 Figure

Claims (1)

[Claims] 1. A scanning pulse is generated in a circuit that generates a scanning voltage for an active matrix liquid crystal display, which consists of multiple scanning wirings, multiple signal wirings that intersect with them, and TFT elements formed at the intersections of these wirings, and stacking liquid crystals. For the output of one stage of the shift register circuit, a plurality of sets of two TFT elements are connected, and two-phase clock voltages from among the same number of multiphase clock voltages as the number of sets are connected to one set. 1. A scanning circuit, which is connected to two TFTs respectively, and generates a scanning voltage obtained by temporally dividing a one-stage shift register circuit by the number of phases of a multiphase clock.