JPH08320670A - Driving circuit for matrix type picture display device - Google Patents

Abstract

PURPOSE: To suppress flicker of a display picture by accumulating electric charges generated in an ON period of a first switching element in a channel section of a second switching element. CONSTITUTION: In a driving circuit 21, a delay circuit D delays a sampling signal of which polarity is reversed by an inverter IN by the prescribed time W2 being shorter than an ON period Wl of a sampling signal, and gives it to a gate of a transistor Q for compensating electric charges. On the other hand, Variation is caused in a range of a time W3 by dispersion and the like of characteristics of transistors constituting a buffer B and the inverter IN, for a sampling signal from a scanning circuit 22. Owing to this, the time W2 is selected to a time, for example W1/2, in which a sampling signal to the transistor Q for compensating electric charges can be raised to ON after a sampling signal is surely raised to OFF even if variation is caused in a range of the time W3 basing a signal shown in γ1 as a reference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device such as a liquid crystal display device in which pixel electrodes are arranged in a matrix.
The present invention relates to a circuit for outputting a gradation signal corresponding to a display image to be applied to a pixel electrode, and particularly to a drive circuit using polycrystalline silicon formed at a low temperature.

[0002]

2. Description of the Related Art For example, a TFT (Thin Film Transistor) liquid crystal display device is an example of the above-mentioned matrix type image display device, and in order to drive each pixel electrode arranged in a matrix, a plurality of scanning signals arranged orthogonal to each other. The TFT is formed at each intersection of the line and the data signal line.
An image is obtained by accumulating the gradation signal from the data signal line in the sample hold capacitor only while T is turned on by the selection signal from the scanning signal line, and applying the inter-terminal voltage of the capacitor to the pixel electrode. It is to display. Therefore, a drive circuit is required which discretizes image signals continuous in the time axis direction at a predetermined cycle, rearranges them in a spatial one-dimensional direction, and outputs them as gradation signals to the data signal lines.

FIG. 9 is a block diagram showing a part of the configuration of a typical prior art drive circuit 1 for outputting a gradation signal to such a matrix type image display device. From the scanning circuit 2 implemented by a shift register or the like to a plurality of sampling signal lines s1, s2, ... (Indicated by reference numeral s when collectively referred to), at predetermined intervals and between the sampling signal lines s. The sampling signals are sequentially output so that the ON periods do not overlap with each other.

The sampling signals of the respective sampling signal lines s are respectively passed through buffers b1, b2, ... (Indicated by reference numeral b) to switch transistors sw1, sw2 ,.
(Indicated by) is given to the gate During the ON period of the sampling signal, the voltage of the image signal line h is applied to the capacitive loads c1, c2, ... (Parentally indicated by reference numeral c when parasitic) on the data signal line via the switch transistor sw. It will be written.

Charge compensation transistors q1, q2, ... (Indicated by reference numeral q when collectively referred to) are provided in association with the respective switch transistors sw. The gate of the switch transistor sw is connected to the scanning circuit 2 from the sampling signal line s via the buffer b, the drain is connected to the image signal line h, and the source is connected to the capacitive load c. On the other hand, the gate of the charge compensating transistor q is connected to the sampling signal line s via inverters in1, in2, ... (Indicated by reference numeral in when collectively referred to), and the drain and source thereof are connected to the switch transistor sw and the capacitance. Are connected to lines k1, k2, ... Connecting to the sexual load c. The terminal voltage of each capacitive load c is output to the pixel driving TFT via the data signal line (not shown) as the gradation signal.

In the drive circuit 1 configured as described above, the switch transistor sw has the structure shown in FIG.
As shown by, electric charge is generated in the channel portion while the switch transistor sw is conducting. As shown in FIG. 10B, when the switch transistor sw is cut off, almost half of the electric charge flows through the image signal line h to the image signal source side having low impedance and is removed, and the remaining electric charge is high. It will flow to the side of the capacitive load c of the impedance.

Therefore, conventionally, the charge compensating transistor q is provided so that the charge that is about to flow from the switch transistor sw into the capacitive load c is absorbed in the channel portion of the charge compensating transistor q. There is.
In this way, the electric charge stored in the capacitive load c can be held constant before and after the OFF timing of the switch transistor sw, and the flicker of the display image can be suppressed.

[0008]

In the drive circuit 1 of the prior art as described above, a pair of switch transistors sw is formed.
The charge compensation transistor q is turned on / off by the sampling signal given from the sampling signal line s.
Since it is driven by FF, the buffer b is used to drive the buffer shown in FIG.
With respect to the sampling signal given to the switch transistor sw as shown in (1), the sampling signal given to the charge compensating transistor q via the inverter in A phase difference may occur as shown in FIG.

That is, the switch transistor sw
The signal indicated by the reference numeral α1 synchronized with the sampling signal for the signal is advanced as shown by the signal indicated by the reference numeral α2 or delayed as shown by the signal indicated by the reference numeral α3. In particular, as indicated by reference numeral α2, when the rising timing of the sampling signal to the charge compensation transistor q is faster than the falling timing of the sampling signal to the switch transistor sw, the charge is already generated at the OFF timing of the switch transistor sw. The compensation transistor q accumulates charges due to the gradation signal.

Therefore, the electric charge generated in the switch transistor sw as shown in FIG. 10 (a) directly flows into the capacitive load c, and the flicker having different levels depending on the maximum amplitude of the gradation signal is generated. There is a problem that it will occur. That is, the smaller the maximum amplitude of the gradation signal, the greater the influence of the charges, and the higher the flicker level.

In particular, when the semiconductor layer of the switch transistor sw is made of polycrystalline silicon,
When driving a capacitive load c having the same capacitance, the variation of the flicker level with respect to the level of the data signal becomes very large. This is because polycrystalline silicon has a lower electron mobility than single crystal silicon, and therefore, when driving the capacitive load c having the same capacitance, the area of the channel portion is large and the characteristics vary. Because it will also grow.

Therefore, another prior art for solving such a problem is disclosed in Japanese Patent Laid-Open No. 4-179996.

FIG. 12 shows another prior art drive circuit 1 described above.
9 is a block diagram showing the configuration of a part of FIG.
The configuration is similar to that shown in, and the corresponding portions are denoted by the same reference numerals and the description thereof is omitted. In this drive circuit 11, each switch transistor sw is turned on / off by a sampling signal from the corresponding sampling signal line s.
Driven. However, the charge compensation transistor q
Then, the sampling signal line for the switch transistor of the next stage, that is, in the case of the charge compensation transistor q1, the sampling signal of the sampling signal line s2 is inverted by the inverter in1 and used for ON / OFF driving.

Therefore, for example, the sampling signal line s
When the sampling signal of 1 is shown in FIG.
The sampling signal of the sampling signal line s2 is shown in FIG.
As shown in (b), the sampling signal line s1
Rises within the ON period w1 of the sampling signal line of
N periods need to overlap. As a result, FIG.
As shown in (c), even if the signal indicated by reference symbol β1 synchronized with the sampling signal is advanced as indicated by reference symbol β2 or delayed as indicated by reference symbol β3, The rising timing of the sampling signal to the charge compensation transistor q can be surely delayed from the falling timing of the sampling signal to the switch transistor sw to absorb the charges.

However, in this conventional technique, in order to overlap the ON periods of the sampling signals between the adjacent sampling signal lines s, the image signal as shown in FIG. As shown in (c), the sampling signal is divided according to the sampling signal, and the sampling signal lines s are divided into a plurality of groups according to the division, and in FIG. 12, two groups are provided, and a dedicated image signal line is provided for each of the two groups. It is necessary to transmit the image signal via h1 and h2. Therefore, a new problem arises that the circuit scale of the external circuit that processes the image signal becomes large.

It is an object of the present invention to reliably remove the charge generated in the switching element for sampling the gradation signal to be output to the signal line with a simple structure and suppress the occurrence of flicker on the display image. It is to provide a drive circuit for a matrix type image display device.

[0017]

According to a first aspect of the present invention, there is provided a matrix type image display device driving circuit, wherein a plurality of signal lines formed corresponding to pixel electrodes arranged in a matrix are connected to the pixel electrodes. In a matrix type image display device drive circuit that outputs a gradation signal corresponding to a display image to be applied, a capacitive load that is provided corresponding to each of the signal lines and outputs the gradation signal, A first switching element, which is provided individually corresponding to the capacitive load and applies an image signal corresponding to the display image to the capacitive load only while the sampling signal is ON, and for each of the signal lines. The scanning circuit that outputs the sampling signal for defining the sampling timing so that the ON periods do not overlap each other, and the sampling signal are the O of the sampling signal. A delay means for delaying and outputting by a predetermined time shorter than the period, and a source electrode and a drain electrode connected to a line between the first switching element and the capacitive load, and responding to a sampling signal from the delay means. In addition, the first switching element includes a second switching element which performs an inverted switching operation.

Further, in the matrix type image display device drive circuit according to the invention of claim 2, the delay means creates a delay signal by delaying the sampling signal by the predetermined time, and the delay signal creating means. Latching means for latching the sampling signal in response to the signal.

Further, in the drive circuit for a matrix type image display device according to a third aspect of the present invention, the delay means is an even number of inverters connected in cascade.

According to a fourth aspect of the present invention, there is provided a drive circuit for a matrix type image display device, wherein a display image to be applied to the pixel electrodes is provided to each of a plurality of signal lines formed corresponding to the pixel electrodes arranged in a matrix. In a drive circuit for a matrix type image display device that outputs a gradation signal corresponding to, a capacitive load that is provided corresponding to each of the signal lines and that outputs the gradation signal, and a capacitive load. Provided individually, only during the period when the sampling signal is ON,
A first switching element that applies an image signal corresponding to the display image to a capacitive load, and a scanning circuit that divides each of the signal lines into a plurality of groups and is provided for each group. In such a scanning, the ON periods do not overlap with each other, and the groups are out of phase with each other by a predetermined time shorter than the ON period, and the sampling signal for defining the sampling timing is output. A source electrode and a drain electrode are connected to a circuit and a line between the first switching element and the capacitive load, and the source electrode and the drain electrode are connected to the latter side and in response to a sampling signal for the first switching element of another group. In addition, the first switching element includes a second switching element which performs an inverted switching operation.

Furthermore, in the drive circuit for a matrix type image display device according to a fifth aspect of the present invention, when the impurity species and their concentrations in the semiconductors forming the first switching element and the second switching element are the same. ,
The area of the channel portion of the second switching element is the first
Is less than half the area of the channel portion of the switching element.

According to a sixth aspect of the present invention, there is provided a matrix type image display device drive circuit, wherein the semiconductors forming the first switching element and the second switching element are:
It is characterized by being polycrystalline silicon.

[0023]

According to the first aspect of the invention, the first signal line is formed for each of a plurality of signal lines which are used for an image display device such as a liquid crystal display device and which are formed corresponding to pixel electrodes arranged in a matrix. In the drive circuit, the image signal corresponding to the display image is written in the capacitive load and the terminal voltage of the capacitive load is output as a grayscale signal during the period when the switching element is turned on by the sampling signal. The charge generated in the channel portion of the first switching element during the ON period of the first switching element is
In removing the switching element at the OFF timing, first, from the scanning circuit, the signal line
A sampling signal for defining the sampling timing is output so that the N periods do not overlap.

Further, the source electrode and drain electrode of the second switching element are connected to the line between the first switching element and the capacitive load. The second switching element includes an inverter and the like, and performs a switching operation that is the reverse of that of the first switching element with respect to the sampling signal. Furthermore, the sampling signal to the second switching element is delayed by the delay means and input by a predetermined time shorter than the ON period of the sampling signal.

Therefore, the sampling time of the first switching element can be set by setting the predetermined time in the delay means in correspondence with the shift of the operation timing between the first switching element and the second switching element. On the other hand, the sampling timing of the second switching element is surely delayed, and the second switching element is certainly in the OFF state at the OFF timing of the first switching element, and the ON period of the first switching element is in progress. The charge generated in the channel
The channel portion of the second switching element can be absorbed at the OFF timing of the first switching element. As a result, regardless of the magnitude of the maximum amplitude of the gradation signal, the gradation signal corresponds only to the level of the image signal, and the flicker of the display image can be prevented.

Further, in realizing such flicker prevention, the number of image signal lines is not increased, and it can be realized with a simple structure.

According to a second aspect of the present invention, the delay means creates a delay signal by delaying the sampling signal by the predetermined time, and a sampling signal in response to the delay signal. And a latching means for latching.

Therefore, only by setting the delay time in the delay signal creating means to a desired value, it is possible to easily perform the fine adjustment of the predetermined time in response to the deviation of the operation timing.

Further, according to the invention of claim 3, the delay means is composed of an even number of inverters connected in series. That is, for example, a delay of several nsec is possible with a single-stage inverter, and an even number of such inverters can be cascade-connected to set a desired delay time.

Therefore, a desired delay time can be obtained with a simple structure.

According to a fourth aspect of the invention, a plurality of signal lines which are used for an image display device such as a liquid crystal display device and which are formed corresponding to pixel electrodes arranged in a matrix are provided. In a drive circuit configured to write an image signal corresponding to a display image into a capacitive load and output a terminal voltage of the capacitive load as a gradation signal during a period in which the switching element 1 is turned on by a sampling signal, The charge generated in the channel portion of the first switching element during the ON period of the first switching element is
In removing the first switching element at the OFF timing, first, the signal lines are grouped into a plurality of groups,
For example, it is divided into two groups such as even-numbered signal lines and odd-numbered signal lines, or a larger number, for example, four groups, and a scanning circuit is provided for each of these groups.

Further, the sampling signals output from this scanning circuit do not overlap each other in the ON periods within each group, and a predetermined time shorter than the ON period between the groups, for example, in the two groups. When there is a certain period, the period is ½ of the ON period, and when the groups are the four groups, the phases are sequentially shifted by ¼ period of the ON period so as to overlap. Furthermore, the source electrode and the drain electrode of the second switching element are connected to the line between the first switching element and the capacitive load. The second switching element includes an inverter and the like, and performs a switching operation that is the reverse of that of the first switching element with respect to the sampling signal. This second switching element is connected to the second switching element on the subsequent stage side of the first switching element to which the second switching element corresponds and to the first group of another group.
The sampling signal is input to the switching element.

Therefore, by setting the predetermined time in correspondence with the shift of the operation timing between the first switching element and the second switching element,
For example, in the case of being divided into four groups, the phase of the sampling signal sequentially shifted by 1/4 of the ON period is output the most of 1/4, 2/4, or 3/4. By selecting the sampling signal having a suitable phase delay period, the sampling timing of the second switching element is reliably delayed with respect to the sampling timing of the first switching element, and the first switching element is turned off. At the timing, the second switching element is surely turned off and the first switching element is turned off.
The electric charge generated in the channel portion during the ON period of the switching element can be absorbed by the second switching element. As a result, regardless of the maximum amplitude of the gradation signal, the gradation signal corresponds only to the level of the image signal, and the flicker of the display image can be prevented.

Further, in order to prevent such flicker, it is necessary to provide the scanning circuits for each group, but in order to lower the operating frequency of the scanning circuits against the increase in the number of pixels, the scanning circuits are provided. There is a case in which a plurality of scanning circuits are provided and the scanning circuits are operated in a mutually offset manner. In such a case, it is not necessary to provide a special configuration.
It can be realized with a simple configuration. Also in this case,
For example, in the conventional technique shown in FIG. 12, four image signal lines are required when the number of scanning circuits is two, but
In the present invention, the number of image signal lines can be reduced to two, the number of image signal lines can be reduced, and external circuits such as an image processing circuit for processing an image signal can be reduced.

According to the invention of claim 5, the first
Channel of the charge generated in the channel portion when the impurity species and their concentrations in the semiconductors forming the switching element and the second switching element are the same, that is, during the ON period of the first and second switching elements. When the amount per unit area of the parts is the same, the area of the channel part of the second switching element is set to half or less of the area of the channel part of the first switching element.

On the other hand, theoretically, the electric charges accumulated in the channel portion of the first switching element when it is turned on half flow to the image signal source side for supplying the image signal and half to the second transistor side. It will be. However, in reality, since the sampling signal changes transiently, there is a slight delay time until the first switching element is turned off, and therefore the current flows to the high-impedance second switching element side. Charge may flow to the low impedance image signal source side through the first switching element. Therefore, the area of the channel portion of the second switching element is unnecessarily increased by setting the area of the channel portion of the second switching element to half or less of the area of the channel portion of the first switching element. The highest effect can be obtained.

According to a sixth aspect of the invention, the semiconductor forming the first switching element and the second switching element is polycrystalline silicon.

Therefore, the electron mobility is lower than that of single crystal silicon, and when driving a capacitive load having the same capacitance, the area of the channel portion is large and the variation in characteristics is large. In the case of crystalline silicon, the present invention can obtain a particularly remarkable effect.

[0039]

1 to 4 of the first embodiment of the present invention.
The explanation is based on the following.

FIG. 1 is a block diagram showing a partial configuration of a drive circuit 21 according to a first embodiment of the present invention for outputting a gradation signal to a matrix type image display device. From the scanning circuit 22 realized by a shift register or the like to a plurality of sampling signal lines S1, S2, ... (Indicated by reference numeral S when collectively referred to), at predetermined intervals and between the sampling signal lines S. The sampling signals are sequentially output so that the ON periods do not overlap with each other.

The sampling signals of the respective sampling signal lines S are respectively passed through buffers B1, B2, ... (Indicated by reference numeral B when they are collectively called), and N-channel switch transistors SW1, SW2 ,. (Denoted by the symbol SW). During the ON period of the sampling signal, the switch transistor SW
The voltage of the image signal line H is written in the capacitive loads C1, C2, ... (Parentally indicated by the reference symbol C) parasitic on the data signal line via.

In connection with each switch transistor SW, N-channel charge compensation transistors Q1, Q2,
... (indicated by reference numeral Q when collectively referred to) are provided. The gate of the switch transistor SW is connected to the scanning circuit 22 from the sampling signal line S via a buffer B.
, The drain is connected to the image signal line H, and the source is connected to the capacitive load C. On the other hand, the gate of the charge compensation transistor Q has delay circuits D1, D2,
... (indicated by reference numeral D when collectively referred to) and inverters IN1, IN2, ... (Indicated by reference numeral IN when collectively referred to) are respectively connected to the sampling signal line S, and the drain and source are the switch transistor SW and the capacitor. Lines K1, K2, which connect with sexual load C ...
It is connected to the. The terminal voltage of each capacitive load C is output to the pixel driving TFT as the gradation signal via a data signal line (not shown).

In the drive circuit 21 configured as described above, the delay circuit D supplies the sampling signal whose polarity is inverted by the inverter IN to the O of the sampling signal.
It is delayed by a predetermined time W2 shorter than the N period W1 and applied to the gate of the charge compensation transistor Q. Therefore, the operation of the switch transistor SW by the sampling signal to the sampling signal line S is shown in FIG.
2B, the operation of the charge compensation transistor Q is as shown in FIG.

On the other hand, the sampling signal from the scanning circuit 22 fluctuates within the range of the time W3 due to variations in the characteristics of the transistors forming the buffer B and the inverter IN. That is, the scanning circuit 22
When the sampling signal from is directly inverted by the inverter IN and is delayed by the delay circuit D for the time W2, a signal as indicated by reference numeral γ1 is obtained. Or a delay occurs as indicated by reference numeral γ3. Therefore, the time W2 is sampled to the charge compensating transistor Q after the sampling signal surely falls to OFF even if the time W2 fluctuates within the range of the time W3 with reference to the signal indicated by the reference numeral γ1. The time when the signal can be turned on, for example, W1 / 2
To be chosen.

As a result, the charge generated in the channel of the switch transistor SW as shown in FIG. 10A is surely absorbed by the charge compensating transistor Q at the OFF timing as shown in FIG. 10B. To be done. Therefore, even if the maximum amplitude of the gradation signal output to the image signal line H is small, the influence of the electric charge on the capacitive load C is eliminated, and the voltage of the capacitive load C before and after the OFF timing of the switch transistor SW. It is possible to prevent fluctuation, that is, flicker of the displayed image. Further, the prevention of such flicker can be realized by a simple configuration in which only the delay circuit D is added, as compared with the conventional technique shown in FIG.

The transistors SW and Q are formed of polycrystalline silicon having the same impurity species and the same concentration. On the other hand, theoretically, half of the charges accumulated in the switch transistor SW flow to the image signal line H side and the charge compensation transistor Q side, respectively. However, in reality, since the sampling signal changes transiently, there is a delay time from when the switch transistor SW starts to be turned off to when the switch transistor SW is completely turned off. The flowed charges may flow to the low impedance image signal line H side via the switch transistor SW.

Therefore, in the present invention, when the impurity species and the concentrations thereof are equal as described above, the area of the channel portion of the charge compensating transistor Q is set to half or less of the area of the channel portion of the switch transistor SW, and the charge compensating transistor is used. The charge is prevented from flowing into the capacitive load C without unnecessarily increasing the area of the channel portion of the transistor Q.

Furthermore, such a configuration can obtain a particularly great effect when the drive circuit 21 is formed monolithically on the same substrate as the image display portion of the liquid crystal panel. That is, in the case of such a configuration, since the transistors SW and Q are formed of the polycrystalline silicon, the transistors SW and Q have the same capacitance due to the lower electron mobility as compared with single crystal silicon or the like. This is because when the capacitive load C is driven, the area of the channel portion is large, and thus the amount of accumulated charges is large and the characteristics of the transistors vary widely.

It should be noted that the delay circuit D is specifically an even number of inverters G formed of, for example, a field effect transistor having a CMOS (complementary metal oxide semiconductor) structure.
1, G2, ... G (2n) (n is a natural number) may be cascade-connected to each other as shown in FIG. In this case, for example, one inverter can delay a few nsec, and therefore, the delay circuit D can be easily configured by combining an even number of inverters for a desired delay time corresponding to the time W2. be able to.

As another example of the delay circuit D, as shown in FIG. 4, a latch circuit F realized by a D flip-flop or the like is provided for each charge compensation transistor Q individually. The latch timings thereof may be controlled by the control signal generation circuit 25.

That is, in the control signal generating circuit 25, the sampling signal lines S1, S2 from the scanning circuit 22 are provided.
Each time a sampling signal is output to ..., The sampling timing signal is input, and the control signal generation circuit 25 delays the rising timing of the sampling timing signal by the time W2 and then outputs the control signal to the control signal line 26. Is output. Each latch circuit F latches and holds the inverted sampling signal from the inverter IN at the timing of the control signal.

Therefore, the delay time in the control signal generating circuit 25 can be finely adjusted according to the characteristics of the inverter IN.

The second embodiment of the present invention will be described below with reference to FIG.

FIG. 5 is a block diagram showing the configuration of a part of the drive circuit 31 of the second embodiment of the present invention. This embodiment is similar to the above-mentioned embodiment, corresponding parts are designated by the same reference numerals, and description thereof will be omitted.

It should be noted that the drive circuit 21 described above has a so-called NMOS structure in which the switch transistor SW is composed of only n-type field effect transistors.
This liquid crystal display device 31 has n-type switch transistors SW1, SW2, ...
P driven by sampling signals from N2, ...
Type switch transistors SWa1, SWa2, ... Are connected in parallel, which is a so-called CMOS structure. Correspondingly, the charge compensation transistors Q1, Q2, ...
, Are connected in parallel, and the sampling signals via the buffers B1, B2, ... Are supplied to the charge compensation transistors Qa1, Qa2 ,.
Have been input respectively.

As described above, the conductive type of the switch transistor may be an optimum type based on the threshold voltage of switching required for each switch transistor, electron mobility, or manufacturing process.

The third embodiment of the present invention will be described below with reference to FIG.

FIG. 6 is a block diagram showing a partial configuration of the drive circuit 41 of the third embodiment of the present invention. In the drive circuit 41, the plurality of switch transistors SW are divided into two groups of an odd number and an even number in the sampling direction (from left to right in FIG. 6).
The sampling signal lines Sa1 and S1 from the scanning circuit 22a are connected to the odd-numbered switch transistors SW1, SW3 ,.
A sampling signal is supplied via a3, ..., Against this, an even-numbered switch transistor SW
A sampling signal is input from the scanning circuit 22b to the SW2, SW4, ... through the sampling signal lines Sb1, Sb4 ,.

Further, to the gate of the charge compensating transistor Q, a sampling signal for the switch transistor of the other group is provided at a stage subsequent to the switch transistor SW to which the charge compensating transistor Q corresponds and via the inverter IN. Has been entered. Furthermore, from the scanning circuit 22a to the sampling signal lines Sa1, Sa3, ...
The sampling circuit 22 outputs the sampling signal to the scanning circuit 22.
The sampling signals output from b to the sampling signal lines Sb2, Sb4, ... Are overlapped with each other while being shifted by the time W2, and are not overlapped with each other in each group.

Therefore, a switch transistor,
For example, when the operation of SW1 is shown in FIG. 2A, the operation of the charge compensation transistor Q1 corresponding to the switch transistor SW1 is delayed by the time W2 as shown in FIG. 2B. Therefore, at the OFF timing of the switch transistor SW1, the charge compensation transistor Q1 is in the OFF state, and the charge generated during the ON period of the switch transistor SW1 can be reliably absorbed and removed.

When the switch transistor SW is driven by the two scanning circuits 22a and 22b as in this embodiment, two image signal lines H1 and H2 are required, and an image signal source (not shown) is provided. Need to output the image signal in synchronization with the sampling signal from the scanning circuit 22a or 22b of the group corresponding to the image signal lines H1 and H2.

However, such a configuration is a method conventionally used in the case where a plurality of scanning circuits are provided in accordance with an increase in the number of pixels, and the operating frequency of the scanning circuits is suppressed. In comparison with the conventional technique shown in FIG. 12, when two scanning circuits are provided as in the present embodiment, four image signal lines are required in the conventional technique, whereas this embodiment is different from the conventional technique. In the example, the number can be two. Similarly, when each switch transistor SW is divided into three groups, six data signal lines are required in the conventional technique, whereas this can be suppressed to three in this embodiment. Thus, it is possible to reduce the number of image signal lines as compared with the conventional technique. Further, by doing so, the number of external circuits such as an image signal processing circuit for processing an image signal can be reduced as compared with the conventional technique.

The fourth embodiment of the present invention will be described below with reference to FIG.

FIG. 7 is a block diagram showing the structure of part of the drive circuit 41a according to the fourth embodiment of the present invention. In this embodiment, the switch transistors SW are divided into four groups, and the scanning circuits 22a and 2 for each group.
2b, 22c and 22d are provided. With respect to the sampling direction, the (4i + 1) th (i = 0, 1,
2, ...) The switch transistor SW (4i + 1) is
The image signals on the image signal line H1 are sequentially and selectively driven by the scanning circuit 22a to be applied to the capacitive load C (4i + 1). Similarly, the switch transistor SW (4i +
2), SW (4i + 3), and SW (4 (i + 1)) are sequentially and selectively driven by the scanning circuits 22b, 22c, and 22d, respectively, and the image signals on the image signal lines H2, H3, and H4 are loaded by the capacitive load C. (4i + 2), C (4i + 3), C
(4 (i + 1)).

Each scanning circuit 22a, 22b, 22c, 22
d outputs the sampling signal so that the ON periods W1 do not overlap with each other within the group and the groups are shifted by ¼ of the ON period W1 between the groups. Further, each charge compensating transistor Q is a sampling signal for the switch transistor of the other group (in the present embodiment, a group two groups behind in the sampling direction by two groups) behind the corresponding switch transistor SW. Driven by.

When the switch transistor SW is divided into a plurality of groups as described above, the OF of the switch transistor SW is changed even if the change occurs in the range of the time W3.
Reliable charge compensation transistor Q at F timing
If the sampling signal can be in the F state,
A sampling signal of the charge compensation transistor Q after the corresponding switch transistor SW and in any other group may be used for driving the charge compensation transistor Q.

The fifth embodiment of the present invention will be described below with reference to FIG.

FIG. 8 is a block diagram showing the structure of a part of the drive circuit 51 according to the fifth embodiment of the present invention. In this embodiment, the structure for controlling the charge compensating transistor Q using the sampling signal for the switch transistor of the next stage as shown in FIG. 6 is used in the CMOS structure as shown in FIG. It is a thing. Further, as the PMOS structure, the structure shown in FIG. 6 can be used.

The present invention is not limited to the liquid crystal display device, but can be suitably implemented in a structure in which, for example, an analog signal is sequentially held by a plurality of sample and hold circuits as time passes.

[0070]

As described above, the drive circuit for a matrix type image display device according to the first aspect of the present invention provides a display image for a plurality of signal lines formed corresponding to pixel electrodes arranged in a matrix. In order to absorb the electric charge generated in the channel portion in the ON period of the first switching element that writes the image signal in the capacitive load that outputs the gradation signal in the drive circuit that outputs the gradation signal corresponding to , A second switching element that performs an operation inverted from that of the first switching element is provided between the first switching element and the capacitive load, and the operation of the second switching element is delayed by the delay means. OFF of the first switching element
Make sure that the second switching element is OF
Make it F.

Therefore, the first switching element is turned on.
Even if the electric charge generated in the period flows out at the OFF timing, it can be accumulated in the channel portion of the second switching element, and the flicker of the display image due to the electric charge flowing into the capacitive load can be suppressed. Such flicker can be prevented with a simple structure.

In the matrix type image display device drive circuit according to the second aspect of the present invention, as described above, the sampling signal for the first switching element is delayed to the second
The delay means provided to the switching element is constituted by latch means for latching the sampling signal, and delay signal generating means capable of arbitrarily setting the latch timing in the latch means.

Therefore, the first switching element and the second switching element
The desired delay time can be easily fine-tuned so that the ON timing of the second switching element can be surely made to be after the OFF timing of the first switching element in response to the deviation of the operation timing from the switching element of You can get it.

Further, in the matrix type image display device drive circuit according to the third aspect of the present invention, as described above, the delay means is composed of an even number of inverters connected in series.

Therefore, in the one-stage inverter, a delay of, for example, several nsec is possible, and by connecting an even number of inverters corresponding to a desired delay time, a signal having the same polarity as the sampling signal can be obtained. In addition, a signal delayed by a desired time with respect to the sampling signal can be created with a simple configuration.

Further, in the matrix type image display device drive circuit according to the present invention, as described above, a plurality of signal lines formed corresponding to the pixel electrodes arranged in a matrix form a display image. A plurality of scanning circuits for sampling and applying an image signal to a capacitive load corresponding to each signal line in a drive circuit that outputs a corresponding gradation signal is provided, and the sampling signal from each scanning circuit is supplied to the scanning circuit. In the corresponding groups, the ON periods do not overlap with each other, and the groups are overlapped with each other by being out of phase with each other by a predetermined time shorter than the ON period. The second switching element for absorbing and removing the charge generated in the channel part is connected to the first switching element of the other group at the subsequent stage side. It is driven by a sampling signal from 査回 path.

Therefore, the first switching element and the second switching element
By setting the delay time corresponding to the shift of the operation timing with the switching element of the second switching element, the second switching element is surely in the OFF state at the OFF timing of the first switching element, It is possible to reliably absorb the charge flowing out from the first switching element by the second switching element, and suppress the flicker of the display image. Further, although a plurality of scanning circuits are required, there are cases where a plurality of scanning circuits are provided so that the operating frequency of the scanning circuits can be lowered in response to an increase in the number of pixels. The delay operation of the second switching element can be performed without increasing the number of lines and the configuration of an external circuit for image processing.

Further, in the matrix type image display device drive circuit according to the fifth aspect of the present invention, as described above, the impurity species and their concentrations in the semiconductors forming the first switching element and the second switching element are When they are the same, that is, when the amount of electric charge generated in the channel portion during the ON period is equal per unit area of the channel portion,
The area of the channel portion of the second switching element is half or less of the area of the channel portion of the first switching element.

Therefore, almost half of the charges generated in the channel portion of the first switching element are absorbed by the low-impedance image signal source side that supplies the image signal, and the area of the channel portion of the second switching element is therefore reduced. Has an optimal area for the amount of electric charge flowing into the second switching element side, and the electric charge can be reliably absorbed without unnecessarily increasing the area of the channel portion.

In the matrix-type image display device drive circuit according to the sixth aspect of the present invention, the semiconductor forming the first switching element and the second switching element is polycrystalline silicon as described above.

Therefore, a large area is required for the channel portion due to the low electron mobility compared with single crystal silicon and the like, so that the amount of charges accumulated in the channel portion increases. The present invention can exhibit particularly remarkable effects in such a polycrystalline silicon semiconductor.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a part of a drive circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the drive circuit shown in FIG.

3 is a block diagram showing an example of a specific configuration of a delay circuit used in the drive circuit shown in FIG.

FIG. 4 is a block diagram showing another embodiment of the delay circuit in the drive circuit shown in FIG.

FIG. 5 is a block diagram showing a partial configuration of a drive circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing the configuration of part of a drive circuit according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing a partial configuration of a drive circuit according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram showing a partial configuration of a drive circuit according to a fifth embodiment of the present invention.

FIG. 9 is a block diagram showing a partial configuration of a typical prior art drive circuit.

FIG. 10 is an electric circuit diagram for explaining a problem in the drive circuit shown in FIG.

11 is a waveform chart for explaining the operation of the drive circuit shown in FIG.

FIG. 12 is a block diagram showing the configuration of a part of another conventional drive circuit.

FIG. 13 is a waveform diagram for explaining the operation of the drive circuit shown in FIG.

FIG. 14 is a waveform diagram for explaining the operation of the drive circuit shown in FIG.

[Explanation of symbols]

21 driving circuit 22 scanning circuit 25 control signal generating circuit (delay signal creating means) 26 control signal line 31 driving circuit 41 driving circuit 41a driving circuit 51 driving circuit B buffer C capacitive load D delay circuit F latch circuit G inverter H image signal Line IN Inverter (second switching element) Q Charge compensation transistor (second switching element) S Sampling signal line SW switch transistor (first switching element)

Claims (6)

[Claims] 1. A drive for a matrix-type image display device, which outputs a gradation signal corresponding to a display image to be applied to the pixel electrodes to a plurality of signal lines formed corresponding to the pixel electrodes arranged in a matrix. In the circuit, a capacitive load that is provided individually corresponding to each of the signal lines and that outputs the gradation signal, and a period that is provided individually corresponding to the capacitive load and the sampling signal is ON Only, the first switching element for applying an image signal corresponding to the display image to the capacitive load, and the sampling signal for defining the sampling timing so that the ON periods do not overlap with each other for each signal line. And a delay unit for delaying the sampling signal by a predetermined time shorter than the ON period of the sampling signal and outputting the sampling signal, A source electrode and a drain electrode line between the switching element and the capacitive load is connected, in response to the sampling signal from said delay means, second from the first switching element performs a switching operation by inverting
A driving circuit for a matrix type image display device, comprising: 2. The delay means comprises delay signal generating means for delaying the sampling signal by the predetermined time, and delay means for latching the sampling signal in response to the delay signal. The drive circuit for a matrix type image display device according to claim 1. 3. The drive circuit for a matrix type image display device according to claim 1, wherein the delay means is an even number of inverters connected in cascade. 4. A drive for a matrix-type image display device, which outputs a gradation signal corresponding to a display image to be applied to the pixel electrodes to a plurality of signal lines formed corresponding to the pixel electrodes arranged in a matrix. In the circuit, a capacitive load that is provided individually corresponding to each of the signal lines and that outputs the gradation signal, and a period that is provided individually corresponding to the capacitive load and the sampling signal is ON A scanning circuit that divides each of the signal lines into a plurality of groups and that is provided for each group, and includes a first switching element that applies an image signal corresponding to the display image to a capacitive load. In order to define the sampling timing, the ON periods do not overlap with each other, and the groups are out of phase with each other by a predetermined time shorter than the ON period. A scanning circuit that outputs a sampling signal, a source electrode and a drain electrode are connected to a line between the first switching element and the capacitive load, and the scanning electrode is connected to the second stage and the second electrode of the other group. A drive circuit for a matrix type image display device, comprising: a second switching element that performs a switching operation that is the reverse of the first switching element in response to a sampling signal for the first switching element. 5. The area of the channel portion of the second switching element is the first switching when the impurity species and the concentrations thereof in the semiconductors forming the first switching element and the second switching element are the same. The matrix type image display device drive circuit according to any one of claims 1 to 4, wherein the area is less than half the area of the channel portion of the element. 6. The matrix type image display device according to claim 1, wherein the semiconductors forming the first switching element and the second switching element are polycrystalline silicon. Drive circuit.