JPS6387770A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the ON-state resistance and the spreading of two dimensional direction by forming a semiconductor layer as well as an electrode layer as semiconductor active elements on a thin band, thereby extending the above layers in the longitudinal direction and also, thereby winding the thin band into a spiral form in the length direction, while external terminals are mounted so that they can be extended in the cross direction of the thin band. CONSTITUTION:This device comprises a thin band 1, a first semiconductor layer 3, a second semiconductor layer 4, a third semiconductor layer 5, control electrodes 6 and external terminals 11-13: while the thin band 1 has a prescribed width and length as well as a inflec tion property that is wound into a spiral form in the length direction inside out; the first semiconductor layer 3 that is formed on the surface of thin band by extending in the length direction as well as the second semiconductor layer 4 that is isolated from the layer 3 and in parallel with the layer 3 in reality; the third semiconductor layer 5 that comes in contact with the surfaces of semiconductor layers 3 and 4 and also fills the gap between the above two layers; the control electrode layers 6 that connect to the third layer 5; a plurality of the external terminals 11-13 that extend in the cross direction of the thin band 1 connected to the first and second layers 3 and 4 as well as the control electrodes 6. Accordingly elements having the spreading of two dimensional direction comes to a cylindrical form and reduces dimensions on the substrate to be used exclusively when they are mounted on a print substrate and the like. Thus, such an arrangement helps reduced the ON-state resistance and the spread ing of two dimensional direction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor active device, and particularly to a semiconductor active device with a relatively high current carrying capacity.

(Prior art) For example, semiconductor active elements used for turning on/off the current of solenoids and motors and adjusting the current value are required to have relatively high current carrying capacity and good heat dissipation, and power transistors are often used. used. An example of a power transistor is a metal heat dissipation base 2 as shown in FIG.
A transistor chip 19 is bonded to the drain electrode pin 16 on the heat dissipation base via an insulating sleeve.
The drain electrode and gate electrode on the chip 19 are connected to the and gate electrode pins 17, respectively, and the source electrode on the chip 19 is connected to the source electrode pin 18 soldered to the heat dissipation base.

When the transistor chip 19 is an FET type, and the transistor structure is the same, the on-resistance of the transistor tends to decrease in inverse proportion to the area of the chip. This type of transistor chip uses a so-called wafer made by slicing a silicon single crystal, and the functional area cannot be easily made three-dimensional.Therefore, in order to reduce the on-resistance, it is necessary to A common method was to increase the two-dimensional dimensions.

(Problems to be Solved by the Invention) As the size of the chip increases, the two-dimensional extent becomes larger, requiring a special structure of the transistor container to ensure mechanical safety of the chip. Also, due to the two-dimensional expansion, the transistor container has a large drawing method,
This occupies a large area on the printed circuit board.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor active element with low on-resistance and a small two-dimensional spread.

[Structure of the invention]

(Means for Solving the Problems) A semiconductor device of the present invention has a flexible thin strip having a predetermined width and a predetermined length, and is wound spirally in the length direction with the surface facing inside. ; on the surface of the ribbon.

a first semiconductor layer formed extending in the length direction;
a second semiconductor layer separate from and substantially parallel to the first semiconductor layer;
a third semiconductor layer that is in contact with the surfaces of the semiconductor layer and the second semiconductor layer and fills the space between them; a control electrode layer that is bonded to the third semiconductor layer; and a plurality of external terminals coupled to the control electrode layer and extending in the width direction of the ribbon.

That is, in the semiconductor device of the present invention, a semiconductor layer and an electrode layer as a semiconductor active element are formed by extending in the length direction on a thin strip, and external terminals are attached so as to extend in the width direction of the thin strip. Assume that the belt is spirally wound in the length direction.

(Function) According to this, an element having a two-dimensional spread of width x length becomes a cylinder with the width as the height and a winding diameter equal to the length, and the element has a two-dimensional spread as an active element. Therefore, when installed on a printed circuit board, the area occupied on the board becomes extremely small.

Therefore, the on-resistance is small and the two-dimensional spread is small.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

(Embodiment) FIG. 1 shows the appearance of an embodiment of the present invention. In FIG. 1, numeral 14 is a semiconductor active element, FET, which has a spiral cylindrical shape. The appearance of this FET is shown in Figure 8.
Referring to the figure and FIG. 8, 11 is a spiral cylindrical FE.
Drain electrode bin connected to the drain electrode of T14, 1
2 is a gate electrode bin connected to the gate electrode, and 13 is a source electrode bin connected to the source electrode. In this embodiment, the substrate 1 of the FET 14 is an aluminum thin strip with an insulating film formed on its surface, and its back surface is exposed as the outer surface. The FET 14 is inserted into a cylindrical heat radiator 15 having radiation fins.

The outer surface of the FET 14 is in contact with the inner surface of the round hole of the heat sink 15.

Next, an outline of the manufacturing process of the FET 14 will be explained with reference to FIGS. 2a to 8.

First of all, on the surface of an aluminum ribbon 1 on which an insulating layer 2 is formed (see FIG. 2a), i.e. an insulating layer 2.
A drain region layer 3 is formed in a comb-teeth shape on the surface using amorphous silicon as a raw material. The direction in which the thin strip 1f1 extends like a comb tooth is the length direction of the thin strip 1f1, and the direction perpendicular thereto is the width direction of the thin strip l. In this way, drain region layer 3
Fig. 2b shows a cross section in the width direction in a state in which the wafer is formed.

Next, as shown in FIG. 3a, a source region layer 4 is formed using amorphous silicon as a raw material on the surface of the aluminum ribbon 1, that is, on the surface of the insulating layer 2.

A comb-like shape is formed between the drain regions N3. The cross section in the width direction with the source region layer 4 formed in this way is shown in 3b.
As shown in the figure.

Next, as shown in FIG. 4a, a channel layer 5 is formed using amorphous silicon as a raw material, spanning the drain region layer 3 and the source region layer 4. A channel layer with a required depth is formed.Next, the surface of the channel layer 5 is subjected to insulation treatment to form an insulating layer 5a. FIG. 4b shows a cross section in the width direction with the channel layer 5 and the insulating layer 5a formed.

Next, as shown in FIG. 5a, a gate electrode WJ6 is formed on the surface of the insulating layer 5a of the channel layer 5 above the channel. FIG. 5b shows a cross section in the width direction with the gate electrode Fs6 formed.

Next, as shown in FIG. 6, conductor layers 7, 8 and 91 to 94 for connecting lead electrodes are formed on the drain region layer 3, the source region layer 4, and the gate electrode layer 6.

Next, the entire surface of the ribbon 1 is coated with a protective film 10. FIG. 7b shows a cross section in the width direction in a state where the protective film 10 is covered. Next, as shown in FIG. 7a, the conductor layers 91 to 94 for connecting the extraction electrodes are connected with a small diameter conducting wire 95. A drain electrode pin 11.degree., a source electrode pin 13, and a gate electrode pin 12 are then joined to the conductor layers 7, 8, and 91 for connecting the extraction electrodes.

The plane-developed FET chip (7th
In Fig. a), it is spirally wound around a rod having a predetermined diameter from the source electrode pin 13 side, and when this winding is completed, it becomes a cylindrical FET 14 as shown in Fig. 8. This cylindrical FET1
4 is inserted into the round hole of the radiator 15 (Fig. 1), where the rod is rotated in the direction of unwinding the spiral, and then pulled out. The side surface, ie, the back surface of the ribbon 1, is in close contact with the inner surface of the round hole of the heat sink 15. In this state, depending on the application, the upper and lower openings of the round hole of the heat radiator 15 are sealed with a metal plate or resin.

The manufacturing process described above involves unwinding a thin strip wound onto a reel in predetermined lengths, performing each process at various points along the feed line of the thin strip, and cutting it after each winding of a predetermined length. ,
Since it can be executed by sequentially inserting it into the heat sink 15,
The cost per FET 14 can be significantly reduced.

〔Effect of the invention〕

The semiconductor device of the present invention has a large width x length, that is, a large area as an active element, but since it is wound into a cylindrical shape and has external terminals (pins) erected in the width direction, it can be mounted on a printed circuit board, etc. In this case, the packaging density is extremely high for the area. That is, the on-resistance is small and the mounting area is small.

[Brief explanation of the drawing]

1st I! ! FIG. 1 is a perspective view showing the appearance of an embodiment of the present invention. 2a, 3a, 4a, 5a, 6, and 7a are plan views of the ribbon 1 at various points in the manufacturing process of this embodiment. Figure 2b is a cross-sectional view taken along the nB-IIB line in Figure 2a, Figure 3b is a cross-sectional view taken along the mB-IIIB line in Figure 3a, and Figure 4b is a cross-sectional view taken along the line nB-IIIB in Figure 2a.
Fig. 5b is a sectional view taken along the line IVB-fVB of Fig. 5a, Fig. 7b is a sectional view taken along the line IVB-■B of Fig. 7a.
FIG. FIG. 8 is a perspective view showing the appearance of this embodiment of the present invention before being inserted into the heat sink 15. FIG. FIG. 9 is a plan view of a conventional power transistor. 1: Thin strip 2: Insulating layer 3 Nidorain region layer (first semiconductor layer) 4: Source region layer (second semiconductor M) 5: Channel layer (third semiconductor layer) 5a: Insulating layer
6: Gate electrode N1 (control electrode layer) 7, L 9t~9
3: Conductor layer 95: Thin conductor wire 10: Protective film 11 Nidrain electrode pin (external terminal) 12: Gate electrode pin (external terminal) 13: Source electrode pin (external terminal) 14: Spiral FET 15: Heat sink 16 :Drain electrode pin

Claims (2)

[Claims] (1) A flexible thin strip having a predetermined width and a predetermined length and spirally wound in the longitudinal direction with the surface facing inside; a first semiconductor layer formed in an extended manner, and a second semiconductor layer separated from and substantially parallel to the first semiconductor layer; in contact with the surfaces of the first semiconductor layer and the second semiconductor layer and filling the space between them; a third semiconductor layer; a control electrode layer coupled to the third semiconductor layer; a plurality of layers extending in the width direction of the ribbon, each coupled to the first semiconductor layer, the second semiconductor layer, and the control electrode layer; A semiconductor device comprising an external terminal; (2) The ribbon is a metal ribbon whose surface has been insulated.
The semiconductor layer is a drain layer, the second semiconductor layer is a source layer, and the control electrode layer is formed on the surface of the third semiconductor layer through an insulating layer above the gap between the first and second semiconductor layers. The semiconductor device according to claim 1, which is a bonded gate electrode.