JPS6386561A - Storage device - Google Patents

Abstract

PURPOSE:To enhance integration by a method wherein an insulating film is formed on the inner wall of a groove formed in a semiconductor substrate and the gate electrode is formed of a MOS transistor constituting an FF connected at the trench bottom to a grove prescribed voltage source and to a high-resistance load. CONSTITUTION:An N-type diffusion layer 3 is formed on the surface of a P-type epitaxial layer 2 grown on an N-type substrate 1. Another P-type epitaxial layer 4 is formed on the N-type substrate 1, and then an element isolating oxide film 12 is selectively formed, after which a groove 5 for a transistor is provided so deep as to reach the N-type substrate 1. A gate oxide film 6 is formed to cover the inner wall of the groove 5 and the trench 5 is filled with a first polycrystal line Si 7 for the construction of a Vcc electrode. The substrate surface is subjected to gate- oxidation, a gate electrode 22 is built of a second polycrystalline Si 8, N-type diffusion layers 9 are formed for a source and drain, a CVD-SiO2 film 11 is grown, and then a buried contact window 18 is opened. A process follows wherein a third polycrystalline Si is used for the establishment of connection between cell data storages, an interlayer insulating film 20 is grown on them, a contact window 23 is provided, and then a data line 21 is built of Al.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a resistive load type SRAM (Static Ra
The present invention relates to the structure of a cell (dom^access memory), and particularly relates to a structure that improves its degree of integration.

[Summary of the invention]

The present invention provides a high resistance load type SRAM in which an insulating film is formed on the inner wall of a groove formed in a semiconductor substrate, and a high resistance load is formed in the groove so that it is connected to a predetermined voltage source at the bottom of the groove. The gate electrode of the MOS transistor constituting the flip-flop connected to the high-resistance load is formed in the groove, greatly increasing the degree of memory integration. be.

[Conventional technology]

Depending on the inverter system that configures the memory cell, the SR
AM memory cells are classified into three types as shown in FIG.

The E/D method shown in FIG. 4A uses an inverter with a depletion type MO5 transistor as a load, and was used in early SRAMs. In this method, since the load current of the inverter is large, the current consumption of the memory cell is large, making it difficult to increase the capacity.

The high resistance load method in Figure 4B is the I-transistors Q1 and C2.
is a switching transistor for data transfer, C4
Let ,Q be the drive transistor for the flip-flow knob,
A polysilicon resistor not doped with impurities or slightly doped with impurities is used as the load of the inverter. This resistor has a very high resistance value of several hundred GΩ, and supplies the minimum load current necessary to maintain the high level output of the inverter. Therefore, the current consumption of the memory cell can be significantly reduced compared to the E/D method.

Since a polysilicon resistor originally has a high specific resistance, the area occupied by the resistor may be small. Also, MOS) transistors must be formed on the substrate, but polysilicon resistors are
OS) Since it is possible to form the memory cell on top of the transistor, the memory cell size of the high resistance load method is the smallest compared to other methods.

A CMOS inverter is used for the CMO5 in FIG. 4C. Since only leakage current flows through the CMOS inverter in a stable state, this method is most advantageous in terms of current consumption of memory cells. However, (JIOS
Since the circuit requires a region to separate the nMOS and pH0s, the memory cell size becomes very large.

Of the three methods mentioned above, the high resistance load method, which allows for the largest capacity, is currently the most popular. To reduce power consumption, peripheral circuits are often composed of CMOS and combined. In addition, SRAM4 for ultra-low power consumption applications is also available as a CMO.
The S method is also adopted.

In either system, the number of elements per memory cell is six, which is larger than other memories. Therefore, the physical structure of memory cells is also more complex than other memories.

Figure 2 shows the currently mainstream high-resistance load type SRA.
The plane of the memory cell of M, and the planes A to A of FIG. 2 in FIG.
The cross-sectional structure at ′ is shown. Regarding the planar structure, there is no general memory cell structure, and it depends on the arrangement method of the elements. In FIG. 2.3, (11, []2 is a switching transistor, and the polycrystalline silicon forming the gate electrode becomes a word line. Port 3 and C4 are inverter drive transistors.

As shown in FIG. 2C1 and FIG. 3, the active region 26 of each transistor is formed in a P-well formed on the semiconductor substrate 1 by diffusion.

In FIGS. 2A and 3, a first polycrystalline Si layer 7 is shown, and these layers are used for switching transistors.
2, that is, the word line 22 and the gate electrode 25.24 of the drive transistor 08.04 of the inverter.

The high resistance load is formed of a second layer of polysilicon 8, as shown in FIGS. 2 and 3. Portions other than the load resistance are doped with impurities to have low resistance, and are used as wiring within the memory cell. In these figures, the polycrystalline St layer that is not doped with impurities appears coarse in grain;
The grains in the area doped with impurities are displayed finely.

Although the bit lines are omitted in the plan view of FIG.
The AI wiring 2 is orthogonal to the word line 22 as shown in the figure.
1 is formed. Two trees are formed for each memory cell.

There are various methods for power supply wiring, but in the case of FIG. 2.3, the ycc wiring is formed of the second layer of polysilicon 8, and the edge wiring is formed of a diffusion layer. These wiring lines have a Δ1 line parallel to the hint line, one for each memory cell.
connected to the power supply wiring.

Since the SRAM memory cell does not use any special elements, the cross-sectional structure of the SRAM memory cell is almost the same as that of a normal MO5LS+ except for the addition of a second layer of polysilicon for a load resistance.

As the cross section is shown in Figure 3, the conventional SRAM
A p-type well is formed on a substrate 1, and an nMOS transistor for a memory cell is built into the well. Although not shown in the figure, pl'lO3 used in the peripheral circuit is formed on the substrate. The second layer polysilicon 8 is formed on the insulating film 11 of the transistor 1-, and is connected to other elements by directly connecting to the +'' rain diffusion layer of the transistor. Separate volume No. 3 rLSI Memory, pages 27-28) [Problems to be solved by the invention] 5RA) In order to increase the degree of integration of I, the design rules of conventional cells must be reduced. It was difficult to achieve this by simply doing so. In memory cells, the load resistor is typically formed from a second layer of polysilicon and is formed on top of the transistors, while diffusion layers or heliode contacts are used to connect the four transistors together. Therefore, in the conventional SRAM, there is a problem in that this isolation region occupies a very large area.

[Failure to solve the problem]

In the present invention, in a memory device in which a memory cell is composed of a flip-flop and a switching transistor, and an inverter circuit constituting the flip-flop has a high resistance load, an insulating film is formed on the inner wall of a groove formed in a semiconductor substrate. formed, the high resistance load is embedded in the groove, and the parenthesis is connected to a predetermined voltage source at the bottom of the groove,
The above problem has been solved by providing a memory device characterized in that a gate electrode of a MOS + transistor constituting a flip-flop is formed in the second trench and is connected to the high resistance load.

[Effect]

In the SRAM of the present invention, transistors Q3 and Q4 other than transistors Q, Q2 in the circuit diagram of FIG. The degree of integration is significantly improved compared to the conventional SRA in which all elements were formed.

〔Example〕

The SRAM of the present invention will be explained based on the manufacturing process shown in FIGS.

First, an N-type substrate 1 is used as the substrate 1, and a P-type epitaxial layer 2 is grown thereon. After a P-type epitaxial layer 2 is first grown to a thickness of about 2 μm, an N-type diffusion layer 3 is formed on the surface of the epitaxial layer 2. After this, what cell's G
It becomes an ND electrode. (FIG. 1A) After that, a P-type epitaxial layer 4 of about 2 μm is further grown. Epitaxial layer 2.4 thus created
After forming a selective oxide film 12 for element isolation on a substrate 1 having a substrate 1, a groove 5 for an I transistor is formed in an epitaxial layer 4.
2 to reach the N-type substrate 1. (Figure 1B
) After performing gate oxidation to grow a gate oxide film 6 on the surface of the trench 5, the trench 5 is filled with first polycrystalline Si 7. At this time, if part of the gate oxide film at the bottom of the trench 5 is removed, the first polycrystalline Si 7 will automatically connect to the substrate 1 and become the νcc electrode. (Fig. 1C) Next, gate oxidation is performed again on the substrate surface, and then word line gate electrodes 22 are formed in the usual manner using second polycrystalline Si8, and then N-type diffusion regions 9 for source trains are formed. form. (Figure 1D) Next, CVD5
An iO7 film 11 is grown, and a vertical contact window 18 is opened in this SiO□ film 11. (FIG. 1D) Thereafter, the data holding portions of the cells are interconnected using the third polycrystalline Si layer 13. As a result, transistor Q3
The source contact 14 of the transistor Q1 is connected to the drain contact 15 of the transistor Q1, and the drain contact 16 of the transistor Q4 is connected to the source contact 17 of the transistor Q2. (FIG. 1F) An interlayer insulating film 20 such as PSG is grown thereon, a contact window 23 is opened there, and a data line 21 (bit line) is formed using AI to complete the SRAM of the present invention.

(FIGS. 1G and H) The portion a of the polycrystalline Si layer 70 in FIG. 1G becomes a high resistance portion, and the portion of the second polycrystalline 5iNs becomes a transistor region.

FIG. 1H shows the positional relationship of each part of the SRAM of the present invention.

〔Effect of the invention〕

The following effects can be expected from the memory device of the present invention.

(i) The cell area can be made very small compared to conventional devices.

(ii) Since most of the cells are embedded in the substrate, the level difference on the surface can be reduced. Therefore, buttering becomes easy.

[Brief explanation of the drawing]

FIGS. 1A to 1H are diagrams illustrating the structure of the SRAM of the present invention. FIGS. 2A to 2C are diagrams showing each part of a conventional SRAM. FIG. 3 is a cross-sectional view of a conventional SRAM taken along line AA' in FIG. FIG. 4 is a diagram illustrating three conventional SRAM systems. ■... Substrate 2.4... Epitaxial growth layer 3.9... Diffusion layer 5... Groove 6.10.
11... Oxide film 7... First polycrystalline Si layer 8... Second polycrystalline Si layer 12... Field oxide film 13... Third polycrystalline Si layer 14.15.16.17 ...helisodo contact 18
．． 19... Contact window 20... Interlayer insulating film 21... A/data cotton 22... Word line 23... Data line contact 24... Gate electrode of 04 125...0. Day 1 - Electrode 26... Active region 27... Passivation film

Claims (1)

[Claims] In a memory device in which a memory cell is composed of a flip-flop and a switching transistor, and an inverter circuit constituting the flip-flop has a high resistance load,
An insulating film is formed on the inner wall of the groove formed in the semiconductor substrate,
The high-resistance load is embedded in the groove and connected to a predetermined voltage source at the bottom of the groove, and the flip-flop is connected to the high-resistance load in the groove.
A memory device characterized in that a gate electrode of an OS transistor is formed.