JPS6386200A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten the screening time of an initial failure by separating a memory cell array and peripheral circuits by controlling signals, selecting and driving all row lines simultaneously and enabling the peripheral circuits to be in workable state. CONSTITUTION:During screening process, chip enable signal inversion CE is set to high voltage synchronously with the supply of address signals Ad0-Adn. During the signal inversion CE is high voltage, a memory cell array 10 is separated from a row decoder 15 by the output signal HV of a high voltage detecting circuit 22, and all row lines 12 are driven and voltage stress is applied to a memory cell 11. Peripheral circuits such as an address buffer 14, a row decoder 15, a column recorder/output circuit 16, etc., are enabled to be in workable state by chip selection signal inversion CE*, and voltage stress is applied. Accordingly, the time required for screening process can be shortened.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) This invention relates to a semiconductor memory device, particularly a read-only memory device that is used exclusively for reading data, and to reduce the screening time for initial defects. The present invention relates to a semiconductor memory device.

(Prior Art) In so-called mask ROMs, in which stored data is programmed using a mask during the manufacturing process, the circuit is actually tested at the beginning of the test process immediately after manufacturing to eliminate initial failures. It is operated to apply voltage stress to each element.

By applying voltage stress, transistors with initial failures are destroyed and removed during subsequent functional tests. Such an initial defect discovery process is called a screening process, and is always performed after manufacturing a semiconductor device.

By the way, the mask ROM screening step (1) has conventionally been carried out by inputting an address signal from the outside and sequentially selecting memory cells row by row.

However, as the capacity of ROM increases, the number of row lines also increases, and the time during which voltage stress is applied to memory cells is equivalent to the time during which voltage is applied to the memory device, assuming that the number of row lines is N. It becomes 1/N or less. Therefore, if you try to apply voltage stress to each memory cell for a certain period of time, it will take a long time to apply voltage to the memory device, and as a result, the time required for testing conventional memory devices increases. There is a drawback.

(Problems to be Solved by the Invention) As described above, the conventional storage device has a problem in that the screening process takes a long time.

This invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor memory device that can shorten the time required for the screening process, thereby shortening the test time. .

[Structure of the Invention] (Means for Solving the Problems) A semiconductor memory device of the present invention is provided with a plurality of row lines and a plurality of memory cells dedicated to reading data, each connected to each of the plurality of row lines. A peripheral circuit that selects a memory cell in the memory cell array and reads data based on an address signal, and a peripheral circuit that separates the memory cell array and peripheral circuit based on a control signal, and connects all the row lines. It is comprised of a control means for simultaneously selectively driving and setting peripheral circuits in an operable state regardless of the address signal.

(Function) In the semiconductor memory device of the present invention, the memory cell array and the peripheral circuit are separated based on the control signal, and all row lines are simultaneously selectively driven based on the control signal regardless of the address signal. Based on this control signal, the peripheral circuits are set to an operable state.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the (j4 configuration) of the semiconductor memory device according to the present invention.
This is a memory cell array in which 'tflh memory cells 11 each made of an S transistor are arranged in row and column directions. Memory cells 1 for one row in this memory cell array 10
1 gate is connected to one of the plurality of row lines 12 in parallel. The drains of one column of memory cells 11 in the memory cell array 10 are connected in parallel to one of a plurality of column lines 13 (data lines). The sources of all the memory cells 11 in the memory cell array 10 are commonly connected to a reference potential, for example, ground. Here, when the row lines 12 connected to each of the memory cells 11 are selectively driven, each of the memory cells 11 reads data programmed in advance and outputs it to the corresponding column line 13.

14 is an address signal AdO or A input from the outside.
The complementary row address signals generated by the address buffer 14 are sent to the row decoder 15, and the complementary column address signals generated by the address buffer 14 are sent to the column decoder. /output circuit 16, respectively.

The row decoder 15 selectively drives any one of the plurality of decode output lines 17 based on the row address signal. A two-man powered OR gate circuit 18 is inserted between each decode output line 17 of these row decoders 15 and each row line 12, and each one input terminal of the OR gate circuit 18 that does not have a signal inversion function is decoded. Output line 17
signal is supplied.

The column decoder/output circuit 16 selects one of the plurality of column lines 13 based on the column address signal. Then, only when the output enable control signal OE is supplied from the outside, the data read out to the selected column line 13 is outputted to the outside as D out.

CE is a chip enable control signal supplied from the outside, and this signal CE controls the operation of peripheral circuits other than the memory cell array 10, including the address buffer 14, row decoder 15, column decoder/output circuit 16, etc., inside the memory device. used to control. This signal CE
In normal use, it is set to either the logic "H" level, which corresponds to the normal readout power supply voltage, or the logic "L" level, which corresponds to the ground voltage. is set to a high voltage higher than the normal read power supply voltage.

The chip enable control signal CE from the outside is supplied to one input terminal of the Nant gate circuit 21 via two series-connected inverters 19 and 20, and is also supplied to the high voltage detection circuit 22. There is. This high voltage detection circuit 22 detects the signal CE by using the voltage corresponding to the high voltage state of the chip enable control signal CE as a slice level, and when the signal CE is at the logic 'H' level or the logic 'L' level, A signal HV is generated which has a logic "H" level and becomes a logic "L" level when in a high voltage state. This signal HV is supplied in parallel to each other input terminal having a signal inversion function of the OR gate circuit 18, and is also supplied to the other input terminal of the Nandt gate circuit 21. Then, an inverter 2 inverts the signal of this Nant gate circuit 21.
The output of 3 is used as an internal chip selection signal CE* to be sent to peripheral circuits other than the memory cell array 10, such as address buffer 1.
4, the row decoder 15, column decoder/output circuit 16, etc. are supplied in parallel. The peripheral circuit is set to an operable state only while this internal chip selection signal CE* is active, that is, at "L° level."

Next, the operation of the storage device configured as described above will be explained.

FIG. 2 is a timing chart for explaining the operation when performing a screening process after manufacturing the above-mentioned embodiment device. During this screening process, address signals AdO to Adn are supplied from the outside, and the chip enable control signal CE is set to a high voltage higher than the power supply voltage in synchronization with the supply of the address signals. During the period when the signal CE is at a high voltage, the high voltage detection circuit 22
The output signal HV of "L level" becomes "L level". By inputting this "L level level signal HV to each other input terminal having a signal inversion function of each OR gate circuit 18, the outputs of all OR gate circuits 18 become "H" level. becomes. As a result,
The memory cell array 10 is separated from the row decoder 15 which is a part of the peripheral circuit, and all row lines 12 are driven regardless of the decoding output of the row decoder 15, and the memory cell array 10 connected to each row line 12 is driven. All memory cells 11 are driven. As a result, voltage stress is applied to all memory cells 11 in parallel.

On the other hand, when the signal HV is at the "L" level, the output of the Nant gate circuit 21 is at the "H" level, and the internal chip selection signal C obtained as the output of the inverter 23
E* is "L level", that is, it is activated. Therefore, this internal chip selection signal CE* causes the address buffer 14, row decoder 15, column decoder/output circuit 1
Peripheral circuits such as 6 become operational, and voltage stress is also applied to the elements constituting these peripheral circuits.

Then, the screening process is executed by repeating the same operation as above.

By the way, during this screening process, all the row lines 12 are driven every memory cycle (the time from one address signal change to the next change), so the number of row lines 12 is N. In this case, the time required for voltage stress to be applied to the memory cell 11 can be increased by N times that of the conventional device. Therefore, when voltage stress is applied to each memory cell 11 for a certain period of time during this screening process, the time for which voltage is applied to the memory device can be significantly shortened compared to the conventional method. . As a result, the time required for the entire test can be made much shorter than in the case of conventional equipment.

When the test including the screening process is completed and it is actually incorporated into the system for use, as shown in the timing chart in Figure 3, address signals AdO to Adn are supplied from the outside, and the supply of this address signal is In synchronization, the chip enable control signal CE is set to the "L" level for a predetermined period. During the period in which this signal 1 is set to either the "H" level or the "L" level, the output signal HV of the high voltage detection circuit 22 remains at the "H" level. On the other hand, the output signal of the inverter 20 is the signal C
It changes depending on E. Therefore, internal chip selection signal C
E* changes in the same way as the chip selection signal σ1° input from the outside.

On the other hand, when the signal HV is at the "H" level, the signal of each OR gate circuit 18 changes according to the signal of each decode output line 17 of the row decoder 15. Therefore, only one row line 12 is selectively driven in accordance with the decoded output of the row decoder 15 at that time. Then, the memory cells 11 connected to the selected row line 12 are driven, and the data stored in these memory cells 11 is read out to the column line 13. The column decoder/output circuit 16 selects one of the data from a plurality of cells read onto the column line 13, and the selected data in parentheses is output to the outside based on the output enable control signal OE.

In this way, according to the memory device of the above embodiment, all the row lines 12 are driven in each memory cycle, so the time for applying voltage to the memory device during the screening process is longer than in the past. This can be significantly shortened, and the time required for the entire test can be made much shorter than in the past.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the above embodiment, a case has been described in which data is programmed into the memory cell 11 by changing the threshold voltage. It is also possible to use a memory cell array in which programming is performed by selecting the desired contact formation or the like.

Furthermore, in the above embodiment, the case where the column decoder/output circuit 1B outputs one bit of data during normal read operation was explained, but this is a configuration in which multiple bits are selected and output. You may also do so.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor memory device in which the time required for the screening process can be shortened, and thereby the test time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIGS. 2 and 3 are timing charts for explaining the operation of the apparatus of the above embodiment, respectively. 10... memory cell array, 11... memory cell,
12... Row line, 13... Column line, 14... Address buffer, 15... Row decoder, IB... Column decoder/output circuit, 17... Decode output line, 18...
OR gate circuit, 19.20...inverter, 21.
...Nant gate circuit, 22...High voltage detection circuit. Applicant's agent Patent attorney Takehiko Suzue 1mata

Claims (1)

[Scope of Claims] 1. A memory cell array including a plurality of row lines and a plurality of memory cells dedicated to reading data connected to each of the plurality of row lines, and a memory cell array in the memory cell array based on an address signal. The peripheral circuit that selects and reads data is separated from the memory cell array and the peripheral circuit based on the control signal, and all of the row lines mentioned above can be selectively driven simultaneously regardless of the address signal, and the peripheral circuit can be operated. 1. A semiconductor memory device, comprising: control means for setting a state. 2. The control means is provided between a high voltage detection circuit that detects a high voltage supplied to the chip selection signal input terminal, and the peripheral circuit and the row line, and is configured to detect a high voltage when the high voltage detection circuit detects the high voltage. a first logic circuit that drives all row lines;
2. The semiconductor memory device according to claim 1, further comprising a second logic circuit that generates an internal chip selection signal when a high voltage is detected by the high voltage detection circuit.