JPS6386045A - Chip selection system for dynamic ram - Google Patents

Abstract

PURPOSE:To shorten read/write cycle time by activating a row address strobe RAS signal to a DRAM when an address is fixed and selecting a column address strobe CAS signal with information on a data width. CONSTITUTION:When an access is received from a master connected to a VMX bus, an address decoder 1 asserts a card selection signal at an H level and sends this information to a timing generator 3. While a data width recognizing circuit 2 decodes the desired signal and sends the information on the judged data width to the generator 3. Then the generator 3 asserts the RAS to the chips 4 and 5 of all DRAM based on the information received from the decoder 1 and then asserts the CAS to ships 4 and 5 based on the information received from the circuit 2 respectively.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a dynamic RAM chip selection method,
In particular, the present invention relates to a chip selection method when writing to or reading from a dynamic RAM chip through a VMX bus or a bus having a sequence similar to the VMX bus.

Conventional technology Traditionally, systems using the VMX bus, e.g.

In a system (not shown) consisting of a CPU (here, the CPU is the master), a dynamic RAM, a memory control device, and an input/output device, the memory control device performs a sequence in which data width information is determined after the address is determined. dynamic RAM through a 7MX bus (or a bus with a similar sequence)
When writing to or reading from D-RAM (hereinafter referred to as D-RAM), after the data width information is determined, the D-RAM
The chips were selected. A D-RAM selection method using such a RAS switching method is generally known.

However, when this method is used in the system described above, write and read cycles to the D-RAM do not start until the data width is determined, so the time from address determination to data width determination takes longer than the write and read cycles. In addition, there was a problem in that the read/write cycle time became longer.

An object of the present invention is to solve such conventional problems and provide a dynamic RAM chip selection method that can shorten the write or read cycle when attempting to write or read from a dynamic RAM through a VMX bus in a memory control device. The goal is to provide a method.

Configuration In order to achieve the above object, the dynamic RA of the present invention
M's chip selection method uses a memory control device that controls data writing and reading from a dynamic RAM based on instructions from a host device connected to a bus that has a sequence in which data width information is determined after an address is determined. By activating the row address strobe signal (RAS) for all dynamic RAM chips when the address is determined, and selecting the column address strobe signal (CAS) to be activated based on the subsequent data width information. , is characterized in that it selects the required dynamic RAM chip.

Hereinafter, the configuration of the present invention will be explained in detail using one embodiment.

The overall configuration of this embodiment is similar to the system configuration described in the prior art, so the explanation will be omitted here, and if necessary, please refer to the prior art.

FIG. 1 shows a dynamic RAM showing one embodiment of the present invention.
FIG. 2 is a diagram for explaining a chip selection method of FIG. this is,
It shows a part of the memory control device connected to the VMX bus and the configuration of a D-RAM chip. Further, the part indicated by the broken line indicates the memory control device, and although not shown in the figure, it is assumed that the memory control device includes a refresh circuit and the like.

In Figure 1, 1 is a mask connected to the VMX bus (
When the D-RAM address space is accessed by CPU), CARDSEL (card select signal) is
The address decoder 2 asserts the information to H" level and sends the information to the timing generator 3. The address decoder 2 determines the width of the data to be written/read by decoding the necessary signals, and sends the information to the timing generator 3. Data width recognition circuit to send, 3 is address decoder 1.Data width recognition circuit 2
A timing generator that generates a D-RAM control signal based on information obtained from the D-RAM, 4 and 5 are selected D-RAs.
This is M's chip. Although only two D-RAM chips are shown here, there may be three or more chips.

FIG. 2 is a comparison diagram of the operation timing according to the embodiment of the present invention and the conventional operation timing.

The operation of this embodiment will be described below with reference to FIGS. 1 and 2.

The master (CPU) is a host device connected to the VMX bus.
) to LAS (lower address) and uAS (upper address) from address decoder 1 of the memory control device.
When received, the address is confirmed and CARDSEL is sent.
Let's call it H Lebel. Next, address decoder 1 is CARDS
Send EL ``H'' information to the timing generator 3. In timing generator 3, address decoder 1 to CARDSEL
After obtaining the "H" information, all D-RAM chips 4
．． Assert RASO for 5. After that, DS (
data strobe (LDS, uDS)) is asserted to indicate the data width, i.e. type a to C (where a ”-
'c indicates the type (byte data, word data, long word data, etc.) is determined, and when that information is passed from the data width recognition circuit 2 to the timing generator 3,
The timing generator 3 takes into consideration the timing required by the D-RAM and sets the CAS (column address) “0°°,
'1' is asserted to the D-RAM chip.This CAS is '0'.

Selecting “1” is done by timing generator 3 using type a.
- Determined by the information in C. This results in the same cycle time in the worst case. Furthermore, using the conventional RAS switching method, when DS is asserted with a delay (after the data width is determined) and RASX is asserted, the read/write cycle must be shortened by the time Ll shown in Figure 2. As explained above, according to the present invention, in the memory control device, dynamic R is enabled through the VMX bus.
When writing to or reading from AM, the write or read cycle can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a chip selection method of a dynamic RAM showing an embodiment of the present invention, and FIG. 2 is a diagram comparing the operation timing according to the embodiment of the present invention and the conventional operation timing. 1 Near address decoder, 2: Data width recognition circuit, 3: Timing generator, 4.5: D-RAM chip. Figure 2

Claims (1)

[Claims] (1) In a memory control device that controls data writing and reading from a dynamic RAM based on instructions from a host device connected to a bus that has a sequence in which data width information is determined after the address is determined, all data width information is determined when the address is determined. The row address strobe signal (RAS) is activated for the dynamic RAM chip, and the column address strobe signal (CA) is activated depending on the subsequent data width information.
By selecting S), the required dynamic R
A dynamic RAM chip selection method characterized by selecting an AM chip.