JPS6385523A - Color electrooptic device by ferroelectric liquid crystal - Google Patents

Color electrooptic device by ferroelectric liquid crystal

Info

Publication number
JPS6385523A
JPS6385523A JP61230741A JP23074186A JPS6385523A JP S6385523 A JPS6385523 A JP S6385523A JP 61230741 A JP61230741 A JP 61230741A JP 23074186 A JP23074186 A JP 23074186A JP S6385523 A JPS6385523 A JP S6385523A
Authority
JP
Japan
Prior art keywords
liquid crystal
signal
ferroelectric liquid
gate
forcibly brought
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61230741A
Other languages
Japanese (ja)
Other versions
JPH0827453B2 (en
Inventor
Shunsuke Kobayashi
駿介 小林
Toshinori Tanaka
稔徳 田中
Sadayuki Shimoda
貞之 下田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP61230741A priority Critical patent/JPH0827453B2/en
Publication of JPS6385523A publication Critical patent/JPS6385523A/en
Publication of JPH0827453B2 publication Critical patent/JPH0827453B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3622Control of matrices with row and column drivers using a passive matrix
    • G09G3/3629Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1335Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336Illuminating devices
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003Display of colours
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3685Details of drivers for data electrodes
    • G09G3/3692Details of drivers for data electrodes suitable for passive matrices only

Abstract

PURPOSE:To permit desired color display by providing a period for holding image plane information after writing of said information to a ferroelectric liquid crystal and continuing the light emission of a plane light emitting element during said holding period. CONSTITUTION:An OPEN signal controls the transfer from a writing action to memory action to a driving circuit when the OPEN signal changes from L to H. The signal DATA to be inputted to a segment driving circuit 11 via an OR gate 14 is forcibly brought to the H when the signal OPEN goes to the H. A signal DF is forcibly brought to the L via an inverter 15 and an AND circuit 16. All the segments of an LC panel 12 attain a VDD level as is evident from the segment output truth table. An FLM inputted to a common driver 13 via an OR gate 17 is forcibly brought to the H when the signal OPEN goes to the H. The signal DF is forcibly brought to the H via an OR gate 18. All the common values of the LC panel attain the VDD level at this time. The segments and common values maintain the memory state.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は強誘電性液晶カラー電気光学装置に関する。特
に強誘電性液晶を用いて継時加法混色によるカラーディ
スプレイを提供する強誘電性液晶カラー電気光学装置の
駆動方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ferroelectric liquid crystal color electro-optical device. In particular, the present invention relates to a method for driving a ferroelectric liquid crystal color electro-optical device that uses ferroelectric liquid crystal to provide a color display by time-based additive color mixing.

〔発明の概要〕[Summary of the invention]

本発明は、強誘電性液晶素子の背面に設置された互いに
異なる色の光を発する光源から、前記強誘電性液晶素子
に継時的に異なる色の光を照射することによりカロ法混
色を生じしめる強誘電性液晶カラー電気光学装置におい
て、前記強誘電性液晶素子の画面書き換え後、そのメモ
リ性を利用して画面保持期間を設けて、前記画面保持期
間の間、前記光源から光を照射することにより、輝度の
高いカラー表示を得ることができるというものである。
The present invention produces Calo method color mixture by sequentially irradiating the ferroelectric liquid crystal element with light of different colors from a light source that emits light of different colors installed on the back side of the ferroelectric liquid crystal element. In the ferroelectric liquid crystal color electro-optical device, after the screen of the ferroelectric liquid crystal element is rewritten, a screen retention period is provided by utilizing the memory property of the ferroelectric liquid crystal element, and light is irradiated from the light source during the screen retention period. This makes it possible to obtain a color display with high brightness.

〔従来の技術〕[Conventional technology]

従来から液晶セルをシャッタとして用いて、その背後に
発光素子(例えばLED、CRT等)を設面して継時加
法混合の現象によりカラー表示を実現する発表はなされ
ている。例えばEurodisplay ’84におい
て発表されたPh1fip Ros、Thom、、1s
 Buzak、Rolf Vatneらの7 9 「−
1AFull−Color FieId−3equen
tial Co1or Displayl(1984/
9/18−20)やSID’85で発表された。1la
sebe、Kobayashiらの「が先行文献として
あげられる。
Conventionally, it has been announced that a liquid crystal cell is used as a shutter and a light emitting element (for example, an LED, a CRT, etc.) is provided behind it to realize a color display by the phenomenon of sequential additive mixing. For example, Ph1fip Ros, Thom, 1s announced at Eurodisplay '84.
Buzak, Rolf Vatne et al. 7 9 “-
1AFull-Color Field-3equen
tial Co1or Display (1984/
It was announced at 9/18-20) and SID'85. 1 la
Sebe, Kobayashi et al.'s ``is cited as a prior document.

しかし、同方式を、強誘電性液晶表示素子に応用した場
合の具体的な駆動方法についての開示された発明はない
。そこで、まず従来の強誘電性液晶の駆動方法を説明す
る。強誘電性液晶例えばカイラルスメクチック液晶(以
下SmC” +!:いう)分子の双安定状態を相互に電
気的に切り換えて(以下スイッチングという)駆動する
強誘電性液晶セル(以下単に液晶セルという)及びそ駆
動回路は特開昭61−94026に開示されている。第
2図に従来の液晶セルの斜視図を示す。1−1は対向配
置している一対の基板である。2−2は基板内平面に設
けられた一軸性又はランダム水平配向膜である。3は配
向膜2−2によって狭さまれたSmC”薄膜であるSm
C”は本来ラセン層構造に有するが配向膜で挾んだ薄膜
にすると図に示すように液晶分子は層をなして水平配向
する。
However, no invention has been disclosed regarding a specific driving method when this method is applied to a ferroelectric liquid crystal display element. First, a conventional method for driving a ferroelectric liquid crystal will be explained. A ferroelectric liquid crystal cell (hereinafter simply referred to as a liquid crystal cell) that is driven by electrically switching (hereinafter referred to as switching) the bistable states of ferroelectric liquid crystal molecules, such as chiral smectic liquid crystal (hereinafter referred to as SmC"+!); and Its driving circuit is disclosed in Japanese Patent Laid-Open No. 61-94026. Fig. 2 shows a perspective view of a conventional liquid crystal cell. Reference numeral 1-1 indicates a pair of substrates facing each other. Reference numeral 2-2 indicates a substrate. It is a uniaxial or random horizontal alignment film provided on the inner plane. 3 is a SmC" thin film narrowed by the alignment film 2-2.
C'' originally has a helical layer structure, but when it is made into a thin film sandwiched between alignment films, the liquid crystal molecules form layers and are horizontally aligned as shown in the figure.

しかしながらsmc”l膜3を上部からみると分子軸が
層の法線4に対して0傾いている。この位置は2通りあ
り第1の安定状態5と第2の安定状態6である。ところ
でSmC”分子は分子軸に直交する向きに自発分極7を
有する。自発分極7の方向は基板1に垂直でありかつ、
双安定状態間で逆極性となっている。従って所定の極性
のパルスを印加することにより安定状態を相互にスイッ
チングすることができる。8−8は互いに直交する偏光
軸を有する一対の偏光板であって、複屈折により液晶分
子の第1の安定状態と第2の安定状態を光通過及び光遮
断として識別する光学変換部材である。9及び10は対
向配置された電極でありSmC”に対してパルスを印加
する。
However, when looking at the smc"l film 3 from above, the molecular axis is tilted at 0 with respect to the layer normal 4. There are two positions for this, a first stable state 5 and a second stable state 6. The SmC'' molecule has spontaneous polarization 7 in a direction perpendicular to the molecular axis. The direction of the spontaneous polarization 7 is perpendicular to the substrate 1, and
The polarity is reversed between the bistable states. It is therefore possible to switch between stable states by applying pulses of a predetermined polarity. 8-8 is a pair of polarizing plates having polarization axes orthogonal to each other, and is an optical conversion member that identifies the first stable state and the second stable state of liquid crystal molecules as light passing and light blocking by birefringence. . Electrodes 9 and 10 are arranged opposite to each other and apply a pulse to SmC''.

第3図に電極構成を示す。9は走査電極であり10は信
号電極である。両電極でマトリクスを措成し周知の時分
割駆動が行われる。
Figure 3 shows the electrode configuration. 9 is a scanning electrode, and 10 is a signal electrode. A well-known time-division drive is performed by forming a matrix with both electrodes.

第4図fatは第3図に示すマトリクス画素の一つに印
加される駆動波形の例である。まず最初の選択期間中閾
値以上の波高値Vop及びパルス幅Tを有する交流パル
スを−サイクル加える。全前半パルスP、の極性が液晶
分子を第1の安定状態から第2の安定状態にスイッチン
グする方向にあると仮定すると、後半パルスP2の極性
は逆方向のスイッチング(第2の安定状態から第1の安
定状態へ)を行なう。結果的にはP+パルスのスイッチ
ングは保持さ、れずP2パルスによるスイッチングが常
に有効となる。次に非選択期間中は闇値以下の波高値を
有する交流パルスが印加され先に得られた第1の安定状
態が保存される。以下ここまでの期間を第1フレームと
呼ぶ。
FIG. 4 fat is an example of a driving waveform applied to one of the matrix pixels shown in FIG. First, during the first selection period, an alternating current pulse having a peak value Vop and a pulse width T that is equal to or greater than the threshold value is applied for -cycles. Assuming that the polarity of all the first half pulses P, is in the direction of switching the liquid crystal molecules from the first stable state to the second stable state, the polarity of the second half pulse P2 is in the direction of switching the liquid crystal molecules from the first stable state to the second stable state. 1) to the stable state. As a result, the switching of the P+ pulse is not maintained and the switching of the P2 pulse is always effective. Next, during the non-selection period, an AC pulse having a peak value below the dark value is applied, and the previously obtained first stable state is preserved. Hereinafter, the period up to this point will be referred to as the first frame.

次にP 3. P aパルスを含む第2フレームでは、
P3.P4パルスの波高値は闇値以下でありかつ第1フ
レームに比較して位相が反転している。したがって第1
フレームでP2パルスによって書き込まれた第1の安定
状態は保持される。
Next P3. In the second frame containing the P a pulse,
P3. The peak value of the P4 pulse is less than the dark value, and the phase is reversed compared to the first frame. Therefore, the first
The first stable state written by the P2 pulse in the frame is maintained.

以上が第1の安定状態に書き込みたい画素に印加される
べき波形であるが、第2の安定状態に書き込みたい画素
については、P、、P2パルスの波高値を闇値以下に、
一方P’3.P4パルスの波高値を闇値以上にすれば良
い。すなわち第1の安定状態にすべき画素は第1フレー
ムで、第2の安定状態にすべき画素は第2のフレームで
書き込むという駆動方式のため2フレ一ム分走査するこ
とによって1画面が形成される。したがって両者の間に
は時間的なずれが生じ、2フレーム走査した後では、第
1の安定状態の方が第2の安定状態より1フレームの時
間分だけ長く表示されていることになる。ところで、第
4図(′b)は、第4図(alの波形を印加した時の透
過光特性であるが非選択期間の交流パルスにより透過光
が△Iだけ常に変化している。これは、コントラストの
低下の原因となる。
The above is the waveform that should be applied to the pixel that you want to write into the first stable state, but for the pixel you want to write into the second stable state, set the peak value of the P, P2 pulse below the dark value.
On the other hand, P'3. The peak value of the P4 pulse should be greater than the dark value. In other words, since the driving method writes pixels that should be in the first stable state in the first frame, and pixels that should be in the second stable state in the second frame, one screen is formed by scanning two frames. be done. Therefore, a time lag occurs between the two, and after two frames have been scanned, the first stable state is displayed longer than the second stable state by one frame. By the way, FIG. 4('b) shows the transmitted light characteristics when the waveform of FIG. , which causes a decrease in contrast.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

今、背面に配置せられた平面発光素子の異なった色の1
つが第5図に示されたように前記2フレームの間だけ発
光するとし、かつ第1の安定状態を光遮断状態(以下具
と呼ぶ。)第2の安定状態を光透過状態(以下臼と呼ぶ
。)とする。ここで第3図m行n列のマトリクス配置さ
れたセルの最上段すなわち1行目と最下段すなわちm行
目の画素を考える。いずれも以前の状態が黒でこの2フ
レ一ム間に白に反転すべき画素だとすれば、第1フレー
ムでは黒が保持されており第2フレームで白に反転する
ことになるが、第2フレームの終了までに最上段の画素
が白になっている時間は(2m−1)Tであり、一方、
最下段の画素はTである。ちなみにSmC”のTは20
0〜300 p seeでありこの程度の時間では、透
過してくる発光色を認識することができず、最下段の画
素では所望のカラー表示が得られないという問題点があ
る。
Now, one of the different colors of the flat light emitting elements placed on the back side.
As shown in FIG. 5, the light is emitted only during the two frames, and the first stable state is the light blocking state (hereinafter referred to as the tool) and the second stable state is the light transmitting state (hereinafter referred to as the mortar). ). Here, let us consider the topmost pixel, that is, the first row, and the bottommost pixel, that is, the mth row, of the cells arranged in a matrix of m rows and n columns in FIG. If the previous state of each pixel is black and should be inverted to white between these two frames, then black will be maintained in the first frame and inverted to white in the second frame, but the pixel will be inverted to white in the second frame. The time for the top pixel to become white until the end of two frames is (2m-1)T, and on the other hand,
The bottom pixel is T. By the way, the T of “SmC” is 20.
0 to 300 p see, and within this amount of time, the transmitted emitted light color cannot be recognized, and there is a problem that the desired color display cannot be obtained in the bottom pixel.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、従来の技術の問題点を解決することを目的と
し、強誘電性液晶素子への画面情報書き込み後、そのメ
モリ性を利用して前記書き込んだ画面を保持する期間を
設けて、前記画面を保持する期間の間、平面発光素子の
発光を継続して行なうものである。
The present invention aims to solve the problems of the conventional technology, and after writing screen information to a ferroelectric liquid crystal element, it provides a period for retaining the written screen by utilizing its memory property. The planar light emitting element continues to emit light during the period when the screen is held.

〔実施例〕〔Example〕

第1図に強誘電性液晶素子の駆動タイミングと平面発光
素子の発光タイミングを示す。第1図において、赤に発
光させたい画素を時間への2フレームの第2フレームで
白に書き込む。−万事面発光素子の赤色光源は時間への
間、発光を継続する。
FIG. 1 shows the driving timing of the ferroelectric liquid crystal element and the light emission timing of the planar light emitting element. In FIG. 1, a pixel that is desired to emit red light is written white in the second frame of two frames in time. - In all cases, the red light source of the surface emitting device continues to emit light for some time.

その後、強誘電性液晶素子の駆動回路に画面保持信号(
以下これを0PEN信号と呼ぶ)を送出し、画面を所望
の時間保持している。その保持期間A゛の間も赤色発光
を継続しておく。同様に青に発光させたい画素を時間B
の2フレームの第2フレームで白に書き込み、その間、
青色発光を継続し、0PEN信号が送出され、青色表示
板面が保持されている期間B’C青色発光を継続する。
After that, the screen holding signal (
This is hereinafter referred to as the 0PEN signal) and the screen is held for a desired time. Red light emission is continued during the holding period A'. Similarly, change the pixel you want to emit blue to time B.
Write in white in the second frame of 2 frames, while
The blue light emission is continued, and the 0PEN signal is sent, and the B'C blue light emission is continued during the period when the blue display board surface is maintained.

緑色発光も同様な手順をとり、A、A’、B、B′、c
、c’の周期を繰り返すことによって継時加法混色を行
なう。前記従来例の問題点を指摘したように、最下段の
画素はT時間しか光を透過しなかったが、本発明では、
保持期間A’、B’、C’を設けることによって透過時
間を長くすることができる。この保持期間A’、B′、
C′の時間は0PEN信号のパルス幅によって任意に設
定することができる。したがって、A’=B’=C′の
時間を長くすれば、i3過光量が増加するため輝度の高
いカラー表示が得られるし、A′≠B゛≠C′の関係に
選べば色相を変化させることができる。
The same procedure is followed for green emission, A, A', B, B', c
, c' is repeated to perform additive color mixing over time. As pointed out above, the problem of the conventional example is that the bottom pixel only transmits light for T time, but in the present invention,
By providing retention periods A', B', and C', the transmission time can be lengthened. These retention periods A', B',
The time C' can be arbitrarily set depending on the pulse width of the 0PEN signal. Therefore, if you lengthen the time for A'=B'=C', the amount of i3 excess light will increase, so you can get a color display with high brightness, and if you choose the relationship A'≠B゛≠C', you can change the hue. can be done.

ところで、次に0PEN信号によって画面を保持する方
法について説明する。
By the way, next, a method of holding the screen using the 0PEN signal will be explained.

第6図は5分の1バイアス平均化法を用いて線順次駆動
で白の書き込みをする場合マトリクス電極に印加される
波形の例を示す。φ、は選択信号電極波形で前半■8、
後半VDDが印加される。φ8は非選択13号電極波形
で前半■2、後半V、が印加される。φ、は選択走査電
極に印加される波形で前半■、。、後半VSが印加され
る。φ7は非選択走査電極に印加される波形で前半V4
が、後半v1が印加される。これを信号電極(以下セグ
メントという)の出力真理値表及び走査電極(以下コモ
ンという)の出力真理値表に表すと以下のとおりである
FIG. 6 shows an example of a waveform applied to the matrix electrode when writing white by line sequential driving using the 1/5 bias averaging method. φ is the selection signal electrode waveform, the first half ■8,
The second half VDD is applied. φ8 is a non-selected No. 13 electrode waveform, and the first half ■2 and the second half V are applied. φ is the waveform applied to the selected scanning electrode, and the first half ■. , the second half VS is applied. φ7 is the waveform applied to the non-selected scanning electrode, and the first half V4
However, the second half v1 is applied. This is expressed in the output truth table of the signal electrodes (hereinafter referred to as segments) and the output truth table of the scanning electrodes (hereinafter referred to as common) as follows.

セグメント出力真理値表 コモンの出力真理値表 ここでDATAは駆動回路に入力されるビデオ信号でH
はセグメント選択を、Lはセグメント非ぶ択を示す。F
LMは駆動回路に入力される走査53号でHはコモン選
択を、Lはコモン非選択を示す。DFは駆動回路に入力
される交流化信号であってHは印加電圧波形基本準位の
前半を、しは同じく後半を示す。例えばセグメント出力
真Fl!値表において、DATAがHのときすなわち選
択セグメントには前半V、が後半■。。印加される。こ
れは第6図のφ8である。
Segment output truth table Common output truth table Here, DATA is the video signal input to the drive circuit and is H.
indicates segment selection, and L indicates segment non-selection. F
LM is the scanning number 53 input to the drive circuit, H indicates common selection, and L indicates common non-selection. DF is an alternating current signal input to the drive circuit, H indicates the first half of the fundamental level of the applied voltage waveform, and H indicates the second half. For example, segment output true Fl! In the value table, when DATA is H, the first half of the selected segment is V, and the second half is ■. . applied. This is φ8 in FIG.

さて両真理値表を見ると■。0電位がセグメントとコモ
ンで共通に使われている。そこでセグメントドライバに
入力されるDATA信号を強制的にロジック制御でHと
し、DF倍信号Lとする。するとすべてのセグメントに
は■、が印加される。
Now, if we look at both truth tables, ■. 0 potential is commonly used for segments and common. Therefore, the DATA signal input to the segment driver is forcibly set to H by logic control, and the DF multiplied signal is set to L. Then ■ is applied to all segments.

同時にコモンドライバに入力されるFLM(8号を強制
的にロジック制御でHとし、DF倍信号Hとする。する
とすべてのセグメントにはvlllllが印加される。
At the same time, the FLM (No. 8) input to the common driver is forcibly set to H by logic control, and the DF multiplied signal is set to H. Then, vllllll is applied to all segments.

これにより、両電極は強制的にVII++電位につなが
ることになる。
This forces both electrodes to connect to the VII++ potential.

第7図は前述したマトリクス電橋をvoに強制的に接続
するための駆動回路であり第8図のタイムチャートと併
せて説明する。11はLCパネル12のセグメントを駆
動するセグメントドライバである。必要な電位レベル■
。D%V、を入力するとともに、DATA及びDF倍信
号基づいてφや及びφオを合成して出力する。CL2は
シリアルなりATAをパラレルDATAに直すための高
速クロ7り、CLlは線順次タイミングを制御するクロ
゛フクである。CL + は同期してパラレルDATA
をランチ出力する。13はLCパネル12のコモンを駆
動するコモンドライバである。必要な電位レベルVDD
〜■、を入力するとともに、FLM及びDF倍信号もと
づいてφV及びφ、を合成して出力する。CL + は
線順次タイミングを制御するクロックである。さて、今
0PEN信号がLからHに変化したとする。0PEN信
号は駆動回路に対して書き込み動作からメモリ動作への
移行を制御する信号である。信号0PENがHになると
、オアゲート14を介してセグメントドライバ11に入
力されるDATAは強制的にHとなる。又インバータ1
5及びアンドゲート16を介してDFは強制的にLとな
る。従ってセグメント出力真理値表から明らかなように
、LCパネル12のセグメントすべて■noレベルとな
る。又、0PEN信号がHになると、オアゲート17を
介してコモンドライバ13に入力されるFLMは強制的
にHとなる。又オアゲート1日を介してDFは強制的に
Hとなる。従ってコモン出力真理値表から明らかなよう
にミLCパネル12のコモンはすべてVOOレベルにな
る。以上によりセグメント及びコモンはVDD同電位に
保持されメモリ状態が維持される。
FIG. 7 shows a drive circuit for forcibly connecting the above-mentioned matrix electric bridge to VO, and will be explained in conjunction with the time chart of FIG. 8. A segment driver 11 drives the segments of the LC panel 12. Necessary potential level■
. D%V is input, and φ and φO are synthesized and output based on the DATA and DF multiplied signals. CL2 is a high-speed clock for converting serial or ATA to parallel DATA, and CL1 is a clock for controlling line sequential timing. CL + is synchronous and parallel DATA
Output lunch. A common driver 13 drives the common of the LC panel 12. Necessary potential level VDD
~■, are input, and φV and φ are synthesized and output based on the FLM and DF multiplied signals. CL + is a clock that controls line sequential timing. Now, suppose that the 0PEN signal changes from L to H. The 0PEN signal is a signal that controls the drive circuit to transition from write operation to memory operation. When the signal 0PEN becomes H, the DATA input to the segment driver 11 via the OR gate 14 is forced to become H. Also inverter 1
5 and the AND gate 16, DF is forced to become L. Therefore, as is clear from the segment output truth table, all segments of the LC panel 12 are at the ■no level. Furthermore, when the 0PEN signal becomes H, the FLM input to the common driver 13 via the OR gate 17 is forced to become H. Also, DF is forced to become H through one day of ORGATE. Therefore, as is clear from the common output truth table, all the commons of the MILC panel 12 are at the VOO level. As a result of the above, the segment and common are held at the same potential as VDD, and the memory state is maintained.

このメモリ状態は、第4図(blの状態とは異なり、△
Iの透過光のふれは、生じないため、コントラストの低
下なしに照射された光量を透過させることがきる。
This memory state is different from the state shown in FIG.
Since no fluctuation occurs in the transmitted light of I, the amount of irradiated light can be transmitted without deterioration of contrast.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、各色の発光光源が継
時的に強誘電性液晶素子を透過してくる時間を、画面保
持期間を設けることによって任意に調節することができ
るため、輝度や色相の調節が可能なカラー表示を得るこ
とができるという効果がある。
As described above, according to the present invention, the time during which the light emitting light source of each color passes through the ferroelectric liquid crystal element over time can be arbitrarily adjusted by setting the screen retention period. This has the advantage that it is possible to obtain a color display whose color and hue can be adjusted.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のSmC’の駆動タイミングと平面発光
素子の発光タイミングとを継時的に表わした図、第2図
は従来の液晶セルの斜視図、第3図は従来の液晶セルの
電極配置図、第4図は従来の液晶セルの駆動波形とそ透
過光特性を示す図、第5図は従来のSmC’の駆動タイ
ミング平面発光素子の発光タイミングとを継時的に表わ
した図、第6図はセグメント及びコモンに印加する波形
図、第7図はLCパネル駆動回路図、第8図は、第7図
に示す駆動回路のタイムチャートである。 11・・・セグメントドライバ 12・・・LCパネル 13・・・コモンドライバ !4.15.16,17.18・・・論理回路以上 出願人 セイコー電子工業株式会社 9芝釆の禾品セ、ルー料乎え図 第2図 イ廼来切液晶セlしめ電λ匹ρこ置図 第3図 9芝釆の京品セル渥(動波形及シ3シ5−九符孝生を示
−(7第4図 ψX        φX cPY        φy プ1ヒj[電Aでiス乏゛ひ−イg号唱t?ミE1:卵
力p正「35皮形囚第6図 バ半ル陶”RU匣I各図 第7図 タイムナマート図 第8図
FIG. 1 is a diagram chronologically showing the drive timing of SmC' of the present invention and the light emission timing of the flat light emitting element, FIG. 2 is a perspective view of a conventional liquid crystal cell, and FIG. 3 is a diagram of a conventional liquid crystal cell. Figure 4 is a diagram showing the drive waveform of a conventional liquid crystal cell and its transmitted light characteristics; Figure 5 is a diagram showing the drive timing of a conventional SmC' and the light emission timing of a planar light emitting element over time. , FIG. 6 is a waveform diagram applied to the segment and common, FIG. 7 is an LC panel drive circuit diagram, and FIG. 8 is a time chart of the drive circuit shown in FIG. 7. 11...Segment driver 12...LC panel 13...Common driver! 4.15.16, 17.18...Logic circuits and above Applicant: Seiko Electronics Co., Ltd. Figure 3 Figure 9 Kyoto product cell in Shiba pot (dynamic waveform and graph showing 5-nine mark Takao) (7 Figure 4 ψX φX cPY φy Hi-i g chant t?mi E1: Egg power p-sho "35 skin-shaped prisoner figure 6 Bahanru pottery" RU box I each figure figure 7 Time Namat figure figure 8

Claims (1)

【特許請求の範囲】[Claims] 2枚の透明部材により挟持された強誘電性液晶薄膜から
なる強誘電性液晶素子と、この表示面に互いに異なる色
の光を継時的に照射することができる複数もしくは単一
の光源よりなる平面光源とを具備した強誘電性液晶カラ
ー電気光学装置において、前記強誘電性液晶に、各色の
光源に対応して透過させるべき画面情報を書き込んだ後
に、任意の時間、前記書き込んだ画面を保持することを
特徴とした強誘電性液晶カラー電気光学装置。
It consists of a ferroelectric liquid crystal element consisting of a ferroelectric liquid crystal thin film sandwiched between two transparent members, and a plurality or single light source that can sequentially irradiate the display surface with light of different colors. In a ferroelectric liquid crystal color electro-optical device equipped with a flat light source, after writing screen information to the ferroelectric liquid crystal to be transmitted corresponding to each color light source, the written screen is held for an arbitrary period of time. A ferroelectric liquid crystal color electro-optical device characterized by:
JP61230741A 1986-09-29 1986-09-29 Ferroelectric liquid crystal color electro-optical device Expired - Lifetime JPH0827453B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61230741A JPH0827453B2 (en) 1986-09-29 1986-09-29 Ferroelectric liquid crystal color electro-optical device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61230741A JPH0827453B2 (en) 1986-09-29 1986-09-29 Ferroelectric liquid crystal color electro-optical device

Publications (2)

Publication Number Publication Date
JPS6385523A true JPS6385523A (en) 1988-04-16
JPH0827453B2 JPH0827453B2 (en) 1996-03-21

Family

ID=16912572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61230741A Expired - Lifetime JPH0827453B2 (en) 1986-09-29 1986-09-29 Ferroelectric liquid crystal color electro-optical device

Country Status (1)

Country Link
JP (1) JPH0827453B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02236519A (en) * 1989-03-10 1990-09-19 Idemitsu Kosan Co Ltd Driving method for ferroelectric liquid crystal panel
WO2000008518A1 (en) 1998-08-06 2000-02-17 Citizen Watch Co., Ltd. Ferroelectric liquid crystal display and method for driving the same
US6750874B1 (en) 1999-11-06 2004-06-15 Samsung Electronics Co., Ltd. Display device using single liquid crystal display panel
US6847345B2 (en) 2001-09-27 2005-01-25 Citizen Watch Co., Ltd. Liquid crystal optical device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63113426A (en) * 1986-09-20 1988-05-18 ソーン イーエムアイ ピーエルシー Operation of display device and display device itself

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63113426A (en) * 1986-09-20 1988-05-18 ソーン イーエムアイ ピーエルシー Operation of display device and display device itself

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02236519A (en) * 1989-03-10 1990-09-19 Idemitsu Kosan Co Ltd Driving method for ferroelectric liquid crystal panel
WO2000008518A1 (en) 1998-08-06 2000-02-17 Citizen Watch Co., Ltd. Ferroelectric liquid crystal display and method for driving the same
US6750874B1 (en) 1999-11-06 2004-06-15 Samsung Electronics Co., Ltd. Display device using single liquid crystal display panel
US6847345B2 (en) 2001-09-27 2005-01-25 Citizen Watch Co., Ltd. Liquid crystal optical device

Also Published As

Publication number Publication date
JPH0827453B2 (en) 1996-03-21

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