JPS638478B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display control device for an electronic display panel, and more particularly to an improved display control device for, for example, a batch display system.

FIG. 1 is an illustrative diagram showing one block of an electronic display panel which forms the background of the present invention and in which the present invention can be implemented. This display block B consists of m columns c1 to cm and n rows arranged crosswise.
Contains r1~rn, each of these columns c1~cm and each row r1~rn
Lamps l11 to lmn are independently provided at each intersection with That is, display block B is m×n
The lamps l11 to lmn are arranged and configured.

As shown in FIG. 2a or 2b, the display panel 100 has p display blocks B1 to Bp.
are assembled in series or in parallel.
Therefore, this one-sided display panel 100 has m×n
It includes xp lamps.

Such a display panel 100 displays, for example, one character on one display block, and can display almost any character (letters or figures). Therefore, it is frequently used for displaying various types of information. Further, the display information to be displayed is generally transmitted remotely from a central processing unit (CPU), not shown. The display panel 100 controls lighting or extinguishing of each of the lamps according to the transmitted display information.

The display information from the CPU is "1" or "H" if the lamps l11 to lmn of each block B are individually lit, and "0" if they are off.
Alternatively, as "L", each block is transmitted sequentially in bit series. In addition, the display panel 100 is
A so-called batch display method is common, in which a page's worth of display information is received from the CPU and then displayed all at once. Then, as soon as the display information of the last block Bp is received, it is displayed.

Therefore, in such a conventional batch display method, if there is information to be displayed on a certain display panel, it is necessary to send a signal to turn on or off m x n x p bits each time. I couldn't do that. This number of bits is in one block.
If 240 lamps are installed, a standard display panel with 12 blocks on one screen will have 2880 bits, which may cause a delay in the timing of lighting. Furthermore, when the display panel receives display information for one screen, it immediately displays it (this is determined by the number of bits), but it is not always clear whether all blocks have been sent. Therefore, there is a possibility that erroneous display may occur due to the influence of, for example, line noise.

Therefore, the main object of the present invention is to provide a display control device for an electronic display panel that can eliminate the above-mentioned problems and achieve more reliable display.

To summarize, the present invention is for controlling the display of a terminal device having a display panel made up of a plurality of display blocks according to display information from a central control device, and for displaying character information sent from the central control device. If there is no error, the character information is stored in the data buffer, and each time the character information for one display block is stored in the data buffer, the counting means is incremented, and the central control is performed. The character information stored in the data buffer is determined by determining the display command information sent from the device, and in response to the output of the counting end signal of the counting means and the determination output of the display command information by the determining means. Based on this, the display is controlled so that a plurality of display blocks are lit all at once on the display panel.

The above objects and other objects and features of the invention will become more apparent from the following detailed description with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention. In the configuration, the above-mentioned figures 1 to 2
A display panel 100 as shown in the figure is provided with a display buffer 101 and a lighting/extinguishing control circuit (not shown). Here, when data (display information) is stored in the display buffer 101, the lighting/light-off control circuit immediately controls the display panel 100 based on the display information.
The lamp is configured to turn on or off.

Between this display panel 100 and the CPU 200,
A display control circuit 300 is inserted.

Therefore, the CPU 200 uses a modem (MODEM) 301 included in this display control circuit 300.
and are connected by a wireless or wired data transmission line. The modem 301 is a modulated CPU 2
The display information starting from 00 is demodulated into a digital on/off signal (“1” or “0”) and provided to the serial-to-parallel conversion circuit 302. The display information from the CPU 200 is, for example, one of the blocks shown in FIG.
The bits are transmitted serially, with each row being one word of m bits, and n words of n rows. Therefore,
This serial-to-parallel conversion circuit 302 converts the bit serial signal transmitted from the CPU 200 into m
It converts into a bit parallel signal every xn bits, that is, every block.

One block of bit-parallel display information from the serial-to-parallel conversion circuit 302 is applied to a buffer register 304, an error verification circuit 305, and an information determination circuit 307. At the same time, a word counter 302 is connected to the serial-to-parallel conversion circuit 302, which is, for example, an n-ary counter incremented every word (m bits). Therefore, this word counter 302 is
Each time one block of display information is received from , a count-up signal is derived, and this is given as a trigger to the error verification circuit 305 . Therefore, this error verification circuit 305 verifies whether there is any error in the received display information for each block of display information.

The error verification circuit 305 generates a "correct" signal if there is no error in the received display information for one block, triggers "YES" of the code generator 306 (returns to the CPU 200 as there is no error), and , provides a judgment trigger to the information judgment circuit 307, and provides a count input to the block counter 308. If there is an error, an "error" signal is generated, and the code generator 306 outputs "NO" (an error is detected and the CPU
200). Therefore, the code generator 306 determines that the received display information is
A code signal that indicates "YES" when correct,
In the case of an error, a code signal indicating "NO" is given to the modem 301, respectively. The information determination circuit 307 determines whether one block of bit parallel display information is character information or lighting command information, and if it is lighting command information, derives a high level or "1" as the determination output. However, at other times, a low level or "0" is derived. The block counter 308 is composed of, for example, a p-adic counter, and is incremented every time it receives the count input, that is, every block, and when it has received display information for a p block, that is, one screen, it derives a count up signal. do.

The “correct” signal from the error verification circuit 305 is
Given as one input of AND gate 309,
The other input of this AND gate 309 is supplied with the inversion of the output from the information determination circuit 307.
The output of this AND gate 309 is given as a read trigger to a buffer register 311 which receives display information for each block from the buffer register 309 and has a storage capacity of one page (p blocks). Furthermore, the information determination circuit 30
The decision output from 7 is provided as the other input of an AND gate 310, which receives the count-up signal from the block counter 308 as one input. The output of this AND gate 310 is
It is given as a read trigger for the display buffer register 101 for driving the display of the display panel 100. In such a configuration, FIGS. 1 to 4 are shown below.
Its operation will be explained with reference to the figure.

In operation, the CPU 200 first sends out m.times.n bit serial display information as shown in FIG. 4A for block B1 of the display panel 100 as shown in FIG. Therefore, the serial-to-parallel converter 302 supplies the buffer register 304, error verification circuit 305, and information determination circuit 307 as bit-parallel display information of one block B1. At this time, word counter 3
A count up signal is obtained from 03,
Error verification circuit 305 has been triggered. Therefore, in this error verification circuit 305, the CPU
It is checked whether there is a transmission error in one block of display information sent from 200. If there is no error, a "correct" signal is obtained from the error verification circuit 305, and "YES" of the code generator 306 is triggered. Therefore, modem 30
1, a return signal "YES" as shown in FIG. 4b is sent back to the CPU 200. Further, the "positive" signal is applied as a count input to a block counter 308 and also to an AND gate 309. Therefore, block counter 308 is incremented by one. At this time, the information determination circuit 307 determines that the information of this block B1 from the CPU 200 is not a lighting command, and derives a low level as its output.
Therefore, AND gate 309 is opened and
AND gate 310 is closed. Depending on this
Buffer register 311 from AND gate 309
A read trigger is applied to the buffer register 311, and the display information of the block B1 stored in the buffer register 304 is transferred (read) to the buffer register 311.

Note that when the error verification circuit 305 determines that there is an error and derives an "error" signal, "NO" of the code generator 306 is triggered and the modem 3
01 sends a return signal of "NO" (not shown) to the CPU 200. Along with that,
Without opening the AND gate 309, the display information for one block of the buffer register 304 is
It is not transferred to the buffer register 311, which has a capacity for one page. Therefore, the CPU 200 sends the display information of the same block again, and continues sending the same information until a "YES" return signal is received.

Thereafter, in the same manner, as shown in FIGS. 4a and 4b, blocks B2 and B in FIG.
3,..., All display information of Bp is CPU200
A return signal of “YES” or “NO” is transmitted to this CPU 200. At this time, if the return signal is "NO", the same block of information is repeated as described above.

When the display information up to the last block Bp is transferred to the buffer register 311 in this way,
At this time, block counter 308 derives a count-up signal and closes AND gate 310.

Subsequently, the CPU 200 transmits a lighting command signal in which, for example, all m×n bits are "1" or high level. Therefore, the information determination circuit 307 determines that the display information just received is a lighting command, and generates a high level or "1" as its output. Therefore,
AND gate 309 is closed and this lighting command information is not transferred to buffer register 311.
At the same time, an output is obtained from the AND gate 310,
A read trigger is given to the display buffer register 101. Therefore, the display information for one page of the display panel 100 (blocks B1 to Bp) stored in the buffer register 311 is read into the display buffer register 101 at this timing. And this display buffer register 1
01, next new display information is CPU200
The information is retained until it is transmitted. Therefore, the display panel 100 is driven to display in response to receiving display information for one screen and receiving a lighting command from the CPU 200.

Therefore, for example, when the data line is idle, display information for one page is transmitted from the CPU 200 in advance, and at the time when it should be displayed, the display information is sent to the CPU 200.
If only the lighting command signal is transmitted from 0, it is expected that the line usage efficiency will be improved. At the same time, since the display is immediately performed at the timing when the lighting command signal is received, there is no shift in display timing. Furthermore, since the display information of all blocks B1 to Bp is received without error and also confirmed by the lighting command signal, safety or reliability is increased.

It should be noted that such a display board 100 may be used to display any information other than traffic information, and it goes without saying that a semiconductor light emitting element may be used instead of a lamp as a display element.

As described above, according to the present invention, if there is no error in the character information output from the central control unit, the character information is stored in the data buffer, and the character information for one display block is stored in the data buffer. Based on the character information stored in the data buffer, in response to the fact that the counting means is incremented every time, and the display command information outputted from the central control unit is determined, and the counting means outputs a counting end signal, Since a plurality of display blocks are lit all at once on the display panel, when the character information of all the display blocks is normally stored in the data buffer, the character information can be displayed reliably and safely on the display panel. Moreover, if the character information is stored in advance in the data buffer when the data line is idle, and only the display command information is sent from the central control unit at the time of display, the line usage efficiency can be improved.

[Brief explanation of the drawing]

FIG. 1 is an illustrative diagram showing one block of an electronic display panel which forms the background of the present invention and in which the present invention can be implemented. FIG. 2 is an illustrative view showing the configuration of one display panel. FIG. 3 is a block diagram showing one embodiment of the present invention. FIG. 4 is a waveform diagram for explaining the mode of transmission of display information. In the figure, 100 is a display panel, 101 is a display buffer register, 200 is a CPU, 300 is a control circuit, 303 is a word counter, 304, 31
1 is a buffer register, 305 is an error verification circuit,
307 is an information determination circuit, 308 is a block counter, and 309 and 310 are AND gates.

Claims (1)

[Scope of Claims] 1. A display control device that controls the display of an electronic display panel having a plurality of display blocks according to display information from a central control device, wherein the central control device controls the display of an electronic display panel having a plurality of display blocks. Character information and display command information to be displayed on the blocks are sent out, and the display panel side includes a data buffer for storing character information from the central control unit, and a data buffer for storing character information for one of the display blocks in the data buffer. a counting means that is incremented each time character information is stored; a determining means that determines display command information from the central control device; and a determination device that verifies whether or not there is an error in the character information from the central control device. an error verification means for storing the character information from the central control device in the data buffer in response to the error verification means verifying that there is no error in the character information from the central control device; store control means; and in response to all the character information being stored in the data buffer, a counting end signal outputted from the counting means and a determination output of the display command information by the determining means are given; A control device for an electric display panel, comprising display control means for causing the plurality of display blocks to light up on the display panel all at once based on the character information stored in the data buffer.