JPS638445B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to temperature compensation for a liquid crystal display device that performs display using a multiplex drive method, and an object of the present invention is to provide a liquid crystal display device that can be used in a wider temperature range. Liquid crystal display devices are currently used in many calculators, watches, etc. due to their low power consumption.
However, as these portable devices become more multi-functional and complex, it is desired that liquid crystal display devices be able to display a large amount of diverse information. In particular, the emergence of super LSIs due to recent advances in electronic technology has further strengthened this demand by making it possible to provide multifunctional circuits. A liquid crystal matrix display device is one device that satisfies this requirement, but due to its structure, it is difficult to perform static driving other than creating a transistor in each pixel, and display is usually performed by multiplex driving. For this reason, various drawbacks arise (the following discussion applies to a type of liquid crystal display device in which the contrast is determined by the effective voltage applied to the liquid crystal, but in this application, a typical twisted nematic type liquid crystal display device will be explained). ). That is, in multiplex driving, since the effective voltage E _OFF , which is also in the "OFF" state of the display, is applied to the liquid crystal, a halftone problem occurs. When performing multiplex drive using the so-called voltage averaging method, if the effective voltages when the display is "ON" and "OFF" are each E _ON and E _OFF ,

【formula】

It is expressed as [Formula]. Here, Vp is the peak voltage applied to the liquid crystal,
a is the ratio between the voltage applied to the liquid crystal and the peak voltage Vp when the scanning electrode is in a non-selected state, and is called the bias ratio. N
is the number of digits of multiplex drive, and the reciprocal 1/N is the duty ratio. The ratio of E _ON to E _OFF , E _ON /E _OFF = α, is called the operating margin and is an important factor that affects display quality.

Since it is expressed as [Formula], as the number of digits N increases, α asymptotically approaches 1. Figure 1 shows the effective voltage characteristics of the light transmittance of a TN liquid crystal cell, where curve a is when light is incident on the cell at an angle of 90°, and curve b is when light is incident on the cell at an angle of 40°. It is a characteristic of In curve a,
The effective voltage that gives a light transmittance of 10% of the difference between the light transmittance Isa when the effective voltage _{is 0} and the light transmittance Isa when the effective voltage increases and becomes saturated is the threshold voltage at 90° incidence. It is called Vth90°, and the effective voltage that gives the same transmittance on curve b is called the threshold voltage Vth40° at 40° incidence. Further, the effective voltage that gives a light transmittance of 90% of Isa-I ₀ on curve a is called the saturation voltage Vsa. Generally, Vth40° is better
Lower than Vth90°. Therefore, in order to obtain a high contrast display within a wide viewing angle, E _ON > Vsa,
The condition of E _OFF <Vth40° is required. However, as mentioned above, as the number of digits in multiplex drive increases, the operating margin α decreases, E _ON < Vsa, and the contrast when "ON" decreases.
At low viewing angles when E _OFF <Vth40°, halftones become visible. In particular, since halftones greatly impair the appearance, if you set E _OFF = Vth 40° and drive while suppressing halftones, the contrast of "ON" will decrease somewhat, but it will still be usable for display. However, the Vth40° and Vsa of liquid crystals change depending on the temperature. That is, as shown in Figure 2, as the temperature rises, Vth40° (curve c),
Both Vsa (curve d) decrease monotonically. For example, if Vth40 = E _OFF at room temperature, at high temperature side, E _OFF >
Vth becomes 40° and a halftone appears. Also,
At low temperatures, contrast decreases. When the number of digits of the multiplexer is small, there is a large margin for the conditions of E _OFF < Vth40° and E _ON > Vsa, so there is no effect on the temperature characteristics of the liquid crystal, but as the number of digits increases, temperature compensation becomes necessary. It's coming. An object of the present invention is to solve this problem and provide a liquid crystal display device capable of displaying high quality over a wide temperature range. Temperature compensation is achieved by controlling the effective voltage of the drive using the output from the temperature sensor.
To change the effective voltage, change the parameters of the above equation, but changing the bias ratio a or the number of digits N of multiplex drive does not involve a change in the operating margin α, and the contrast of the display changes significantly. This is an undesirable result. α mentioned above
Since Vp is not included in the equation, α does not change even if Vp is changed, so the display contrast does not change significantly. However, in low power consumption portable devices such as wristwatches,
It is very difficult to change Vp minutely. Generally, wristwatches use approximately 1.5V from a silver oxide battery as a power source, and when a higher voltage is required, the voltage is boosted by a booster circuit. Therefore, although voltages that are integral multiples of 1.5V can be created relatively easily and with low power loss, it is extremely difficult to create intermediate voltages and vary them finely. FIG. 3 is a diagram of a Vp variable circuit using a POSISTOR, which is composed of a battery 1, a POSISTOR 2, a fixed resistor 3, and a liquid crystal drive circuit 4. The terminal voltage E of the battery 1 is divided by the resistance value Rp of the POSISTOR 2 and the resistance value R of the fixed resistor 3, and V=R/R+RpE is supplied to the liquid crystal drive circuit 4 as an output. Here, the internal resistance r0 of battery 1
The input impedance (rin) of the liquid crystal drive circuit 4 was assumed to be infinite. Therefore, temperature compensation can be performed if a POSISTOR with appropriate temperature characteristics of Rp is selected, but in this case, the power consumed by 2 and 3 is E ² /R + Rt, and E is a few volts and R + Rt.
If it is several kilohms, several milliwatts of power will be consumed. Furthermore, it is thought that reducing the variation in temperature characteristics of the POSISTOR 2 will become a problem during mass production. For these reasons, it is difficult to use a method of changing the effective value by controlling Vp in wristwatches. Therefore, the present invention uses a method of changing the effective voltage by changing the driving duty. That is, part of each selection period of the scan electrodes is set to the same potential for all scan and signal electrodes so that no voltage is applied to the liquid crystal, and the effective voltage is increased by lengthening or shortening the period of all non-selection. change. In general, drive duty refers to the ratio of the selection period of one scanning electrode in one frame period, that is, the reciprocal of the number of digits N in multiplex drive. I will use it in a meaningful way. 4-a to f
The figure shows 8-digit multiplex drive, 1/4 bias,
This is an example of scanning electrodes, signal electrodes, and liquid crystal drive waveforms when Vp=6V. Figures 4-a to 4-c show the scanning waveform (Figure 4-a), signal waveform (Figure 4-b), and liquid crystal drive waveform (Figure 4-c) when temperature compensation is not performed. Figures -d to f show the scanning waveform (Figure 4-d) and signal waveform (Figure 4-4) when the effective value is lowered by temperature compensation.
Fig. 4-e) and liquid crystal drive waveform (Fig. 4-f).
The potential of each electrode during the entire non-selection period when no voltage is applied to the liquid crystal may be any potential, but here it is set to 0V. If the ratio of all non-selected periods to one scanning period is η, then the effective voltages E _ON and E _OFF at this time are:

【formula】

Therefore, the same effect as changing the peak voltage Vp can be obtained. Both Vth40゜ and Vsa are high on the low temperature side and decrease as the temperature increases, so reduce the total non-selection period at low temperatures, and increase it as the temperature rises to lower the effective value to compensate for the temperature. Can be done. As mentioned above, temperature compensation can be performed by changing the drive duty, but a temperature sensor is required to control the drive duty. In the present invention, two independent crystal oscillators are used, and two output beat signals of the oscillators are used as temperature sensor outputs. The present invention will be explained in detail with reference to Examples below. Embodiment FIG. 5 is a block diagram of an embodiment of the present invention.
Main oscillation circuit 5, sub oscillation circuit 6, beat generation circuit 7, frequency comparison circuit 8, frequency division circuit 9, AND gate 10, binary counter 11, D type latch 12,
Comparator 13, boundary value setting circuit 14, programmable counter 15, preset counter 16,
It consists of an AND gate 17, a reset flip-flop 18, a liquid crystal drive signal generation circuit 19, a multiplexer 20, and a liquid crystal drive circuit 21. If the crystal oscillators used in the main oscillation circuit 5 and the sub oscillation circuit 6 are A and B, respectively, the oscillators A,
It is assumed that the characteristic of B is _A = _OA −a _A (θ−T _OA ) ² _B = _OB −a _B (θ−T _OB ) ² . Here, θ is the ambient temperature
T _OA , T _OB are the peak temperatures of each oscillator, _OA , _OB are T _OA ,
T _OB is the oscillation frequency, a _A , and a _B are the temperature coefficients specific to the elements. When the temperature coefficients a _A and a B of oscillators _A and _B are equal, and the peak temperature T _{OA of oscillator A is OA ,} the oscillation frequency is equal to _OA . Combine with child A. The beat frequency _B in such a combination is _BE = | _A − _B | = |2a (T _OA − T _OB ) (θ−T _OA ) |, and the beat frequency _BE is proportional to the absolute value of θ − T _OA do. Specifically, the difference in peak temperature between the vibrators A and B is 12 to 13° C., and the difference in oscillation frequency at the peak temperature T _OB < _TOA is approximately 5 ppm. The beat frequency _B when selected in this way is _B = 6.48×10 ^-3 |θ−
It is about T _OA | Hz. The beat generation circuit 7 mainly includes:
A beat signal BT is generated from the outputs _A and _B from the sub-oscillator and inputted to the AND gate 10. AND gate 1
0, the output of the main oscillator 5 is frequency-divided by the frequency divider 9 and the preset counter 15, and the reference signal s and BT are ANDed together and inputted as a clock signal to the binary counter 11. Assuming that the counter 11 is reset before receiving the clock input from the counter 10, the count number N of the counter 11 is proportional to the period of BT, so the following equation is obtained. N=s×1/2 _B =s/2α|θ−T _OA | Here, α is a proportional coefficient of _B with respect to |θ−T _OA |. The data of the count number N of 11 is latched into the D-type latch by the clock immediately after the falling edge of BT. The count number N is compared in a comparison circuit 13 with several boundary values set in advance in a boundary value setting circuit, and temperature compensation data is output. However, the period of BT is |θ−
Since it is a function of T _OA |, if θ=T _OA ±△θ, the same count number N is output. Therefore, θ＞T _OA
It is necessary to determine whether For this purpose, a frequency comparison circuit is installed to compare _A and _B , and _A
> _B , then θ>T _{OA A} < _B , then θ<T _OA . The comparison circuit 13 determines in which region the temperature is based on the output of 8 and the count number. Preset counter 16 presets and counts the data from 13. In other words, when a pulse synchronized with the start of the scanning signal from 9 is input to FF18, 1
8 is in the set state and the output _Q18 is high,
The clock pulse from 9 begins to be output from the output of AND gate 17. counter 16 is 1
It starts counting the data from 3 to the initial value, and when the predetermined output is reached, it outputs a pulse and resets the FF18.
Therefore, if the preset data from 13 is large,
The time that Q ₁₈ in FF18 is high is shorter, and Q ₁₈
If this is used as a control signal for the multiplexer 20 and switched between the output of the liquid crystal drive signal generation circuit 19 and 0V and inputted to the liquid crystal drive circuit 21, the effective value applied to the liquid crystal becomes small. The above is the operating principle of the temperature compensation system of the present invention. The specific temperature compensation value varies depending on the type of liquid crystal, but in this application, it will be explained in detail using a typical liquid crystal for multiplex driving as an example. The above-mentioned Figure 2 shows the liquid crystal display.
This is the temperature dependence of Vth40° (curve c) and Vsa (curve d). Curves c and d are slightly upwardly convex, but for simplicity, they are assumed to be linear. At 0°C, Vth40° = 1.8V, and at 40°C, Vth40° = 1.58V, which is a decrease of about 12% at 40°C. On the other hand, if the frame frequency of AC drive of the liquid crystal is 32Hz, 8-digit multiplex drive, Vp = 6V, a = 4, then at 100% duty, E _OFF = 1.76V, and at 0 to 10°C, E _OFF <Vth is 40° and halftone is not visible.
Halftones are visible at temperatures above 10°C. Therefore, the effective voltage is lowered stepwise to compensate, as shown by curve e in FIG. If you increase the number of stairs and make the steps finer, the accuracy of compensation will increase, but the fifth
It is determined by the clock frequency input to 16 through 9 to 17 in the figure. The upper limit of this clock is 32K.
Hz (accurately 32768 Hz, but abbreviated as such below), the accuracy of compensation is limited. Now, let's consider the number of compensation steps at 32KHz. Since the frame frequency is 32 Hz, the period during which one scanning electrode is selected in one frame period is 32×8=256 Hz. Furthermore, since AC driving is performed, the period in which the voltage applied to the liquid crystal has positive or negative characteristics coincides with a period of 256×2=512 Hz. The effective value is changed by setting the potential to 0V for part of this 512Hz period. 32KHz is 64 times as high as 512Hz, so even if you create 32KHz as 16 clock signals, you can only change it by 1/64.
Since 1/64 = 1.6%, in order to change the 12% difference between the values of 0°C and 40°C of Vth40°, 12÷1.6 = 7.5.Therefore, in 9 steps from 0 to 8, 1 in the middle In the example, it is sufficient to compensate for the temperature in steps of 5°C.
The temperature range for one step was determined as shown in Table 1. Curve c in Figure 2 shows E _OFF when the temperature compensation is performed.
is the compensation curve. Table 1 shows the beat frequency, beat period, and count number N of the counter 11 when the reference signal s=8 Hz. From Table 1, it can be seen that for N247, 22.5θ<27.5. Similarly, if 83N<247, then 17.5<θ<
225, or 27.5<θ<32.5.
The same applies to other count numbers. 14, C ₁ = 247, C ₂ = 83, C ₃ = 50, C ₄ = 36, C ₅ = 28
The boundary values of N and C ₁ are set, and the comparator 13
~16 presets are calculated from the data compared with _C5 and the output of frequency comparison circuit 8.

【table】

[Table] Outputs the test data. For example, if 83N<247 and the output of 8 is hish, 27.5<θ<32.5 and the binary number 6 is output. Since the boundary value of the count number can only be set as an integer, an error occurs between the set temperature range and the temperature range determined from the count number. This error can be reduced by increasing the frequency of the reference signal s, but if it is too high, the counter 11
The number of bits in the latch 12 and comparison circuit 13 increases. Therefore, in the embodiment, s=8 Hz.
The error at this time is less than 0.5°C. Also, _B = β
β of |θ−T _OA | was set to β=6.48×10 ⁻³ , but it varies depending on the combination of vibrators. There are two ways to adjust this variation: change the boundary value setting of the count number N, or change the reference frequency s. To change the boundary value setting, C ₁ to C ₅
data must be set. On the contrary,
The change in the frequency of s is determined by programmable counter 1.
Just change the settings in step 5. Therefore, in the embodiment, the variation in β is adjusted by setting 15. The circuit blocks shown in FIG. 5 include the oscillators 5, 6, counter 11, etc., but there are also special blocks, which will be explained below. FIG. 6 shows a specific example of the beat generation circuit 7 and the frequency comparison circuit 8. flipflop 22~2
5AND gate 26, OR gate 27, D flip-flop 28-31, RS flip-flop 3
2, 33, inverters 34, 35, and a D-type flip-flop 36. The 32KHz output of the main and sub oscillators 5 and 6 is output from the flip-flop 22.
.about.25, each frequency is divided by two stages to obtain an 8KHz signal. This will be explained below using the timing chart shown in FIG. Qs obtained by dividing the output from sub oscillator 6
is input to AND gate 26 and OR gate 27,
An operation is performed between the inverted output of the master of 25 and the D input of FF28 and 30 from 26, respectively.
A ₁ is input from 27, and O ₁ is input to the D inputs of FFs 29 and 31. A ₁ is 8KHz, 3/4 duty O ₁ is 8K
Hz, 1/4 duty signal, the fall of A ₁ is O ₁
The phase relationship is in the middle of the rise of . On the other hand, the output of the main oscillator 5 becomes a _QM signal of 8 KHz and a duty of 1/2, and enters the clock inputs of the FFs 28 and 29. Also, inverters 34 and 35
By passing through, the delayed phase becomes Q _M d and becomes FF3
Enters the clock input of 0 and 31. Now, considering that _A < _B , Q _M is delayed in phase compared to A ₁ and O ₁ , and when the rise of Q _M lags the rise of A ₁ , _{the 28} output of FF28 changes from high to low. Go down. After this, ₂₈ continues to be low, but when the phase of Q _M lags A ₁ by the period of A ₁ = low, and the rise of Q _M is delayed from the fall of A ₁ , ₂₈
becomes high and then remains high until the rise of Q _M lags the rise of A ₁ .
Similarly, for the output of FF29, _Q29 falls when _O1 falls earlier than _QM rises.
When O ₁ rises faster than Q _M rises, Q ₂₉ rises. ₂₈ serves as 32's set input, and _Q29 serves as 32's reset input. The output Q ₃₂ of 32 rises at the same time as ₂₈ falls, and falls at the same time as Q ₂₉ falls. This Q ₃₂ is the beat output, and the AND in Figure 5
It becomes an input to gate 10. FF30 and 31 output 30 because the clock _QMd lags behind _QM .
Q ₃₀ is more than one Q _M clock ahead of ₂₈ . 31
The output Q ₃₁ proceeds similarly from Q ₂₉ . Therefore, FF3
3's output Q ₃₃ is ahead of Q ₃₂ . Conversely, when _A > _B and the main oscillator output phase advances, Q ₃₂ is better.
It rises and falls with a phase that is more advanced than _Q33 .
Therefore, Q ₃₂ is the D input of the D type FF36, and Q ₃₃ is the D input of the D type FF36.
If it is CL input, when _A < _B , output of FF36
Q ₃₆ is always low, and when _A > _B , Q ₃₆ is high, allowing frequency comparison between _A and _B. Next, 19~
The driving portion of the liquid crystal 21 will be explained. FIG. 8 shows a liquid crystal drive signal generation circuit 19, a multiplexer 20,
2 is a diagram of a liquid crystal drive circuit 21. FIG. The part within the broken line with the numeral 19 is a liquid crystal drive signal generation circuit, which is composed of a booster circuit 37 and multiplexers 38 to 40.
This circuit is for Vp = 6V, bias a = 1/4, and the battery voltage of 1.5V is rounded to 3V, 4.5V,
I am getting 6V. These potentials are switched by multiplexers 38 to 40 to perform alternating current driving of the liquid crystal. For example, since the ON level (COM-ON) of the scanning electrode signal is 0V or 6V, 38
, the polarity is switched by a polarity switching signal. The same applies to other COM-OFF, Seg-ON, and Seg-OFF signals. When temperature compensation is not performed, this signal is applied to the liquid crystal drive circuit 16, but in the present invention, multiplexers 41 to 44 are inserted to switch between this signal and 0V. The output of the FF 18 is connected to the control terminals of the multiplexers 41 to 44 for control. FIG. 9 shows a circuit example of the comparator 13, including an 8-bit magnitude comparison circuit 15, a boundary value setting ROM 46, an address counter 47, a shift register 48, a decoder 49, an OR gate 50, and an inverter 51.
It consists of Comparison circuit 45 has an 8-bit configuration and compares N from latch 12 with boundary values C ₁ to C ₅ from ROM 46 to determine that Cx>N (x=1 to 5), Cx=
Outputs three types of output: N, Cx<N. The ROM46 has a parallel 8-bit x 5 configuration with address clock _ACL.
The boundary value Cx set at the specified address of the 3-bit output of the counter 47 synchronized with the rising edge _{of C1}
Outputs C ₅ sequentially from . Therefore, the output of 45 is first the comparison result between N and _C1 , and then the comparison result between _C2 and is sequentially compared and output. At this time, N>Cx,
N=Cx is logically summed by the OR gate 50 and becomes the D input of the shift register 48. That is, Cx
If N, the output of 50 will be high, and 48 will be C ₁ ~
The comparison results of C ₅ and N are stored sequentially in synchronization with the rising edge of A _CL , and the Q output of each stage (from the first stage to S ₅ , S ₄ ,
S ₃ , S ₂ , S ₁ ) are output to the decoder 49.
The decoder 49 outputs preset data (4 bits) of the preset counter 16 from _S1 to _S5 and the output Cf from the frequency comparison circuit 8. Table 2 is
This is a truth table for creating P ₁ to _{P 4} from S ₁ to S ₅ and Cf.
Here, x indicates that it may be either 1 or 0. For example, a decoder that obtains an output of P ₄ will write P ₄ =
Since it satisfies S ₁ , S ₂ , S ₃ , ₄ , ₅ , it becomes as shown in Figure 10. Other P ₁ , P ₂ , P ₃
The same applies to the case shown in FIG. 10. In this way, it is possible to compensate the temperature of the liquid crystal panel with a relatively simple circuit. Crystal oscillator in terms of cost

[Table] However, in twin quartz clocks, which are known to compensate for the temperature of the crystal oscillator itself, the present invention allows high precision, such as the ability to share a part of the oscillator and circuit. Moreover, it is possible to provide a wristwatch with good display quality in a wide temperature range. As described above, the present invention includes a main oscillator, a sub oscillator, a beat signal generating means for generating a beat signal from the oscillation outputs of the main oscillator and the sub oscillator, and a count number proportional to the beat signal at a specific period. counting means for arbitrarily setting the boundary of the count number and outputting a plurality of boundary values; Frequency comparison means for comparing high and low ambient temperatures and outputting the comparison results, comparing the count number from the counting means and the boundary value from the boundary value setting means, and selecting the boundary value closest to the count number. an ambient temperature is specified by the selected boundary value and the comparison result from the frequency comparison means, a comparator that outputs a digital value corresponding to the specified temperature, and a specific scanning period of the liquid crystal display driver. a preset counter that counts the clock pulses of the period and is preset by the digital value from the comparator to determine the initial value for counting the clock pulses; Since the liquid crystal drive circuit consists of flip-flops that are set synchronously, a pulse width is controlled by the output from the flip-flop, and a liquid crystal display is driven by the controlled pulse width, the boundary described above can be avoided. The setting range in the value setting circuit can be set arbitrarily, and it can be confirmed whether a specific boundary value based on a count value proportional to the beat signal is higher or lower than the peak temperature of the oscillator. Therefore, since the relationship between the effective voltage applied to the liquid crystal and the temperature can be set more precisely, it is possible to control the display of the liquid crystal through highly accurate temperature correction.

[Brief explanation of the drawing]

Figure 1: Light transmittance-effective voltage characteristics of a TN liquid crystal cell. Figure 2: Temperature dependence of Vth40° and Vsa. Figure 3: A power supply circuit diagram for driving a liquid crystal using a resistor. 1...Battery, 2...Posistor, 3...Resistance, 4
...Liquid crystal drive circuit. Figures 4-a to c...Scanning without temperature compensation,
Figures 4-a to 4-f are diagrams of signals and liquid crystal drive waveforms. Diagrams of scanning, signals, and liquid crystal drive waveforms during temperature compensation are shown. Figure 5 is a block diagram of the temperature compensation system of the embodiment. 5... Main oscillation circuit, 6... Sub oscillation circuit, 7...
Beat generation circuit, 8... Frequency comparison circuit, 9...
Frequency dividing circuit, 10...AND gate, 11...Binary counter, 12...D type latch circuit, 13...
Comparator, 14... Boundary value setting circuit, 15... Programmable counter, 16... Preset counter, 17... AND gate, 18... Set reset FF, 19... Liquid crystal drive signal generation circuit,
20...multiplexer, 21...liquid crystal drive circuit. FIG. 6: A circuit diagram of the beat generation circuit 7 and the frequency comparison circuit 8. 22-25...FF, 26...AND gate, 2
7...OR gate, 28-31...D type FF, 3
2, 33...NAND latch, 34, 35...Inverter, 36...D type FF. FIG. 7 is a timing diagram of the beat generation circuit 7, and FIG. 8 is a circuit diagram of the liquid crystal drive signal generation circuit 19 and multiplexer 20. 37...Booster circuit, 38-44...Multiplexer. FIG. 9: A circuit diagram of the comparator 13 and the boundary value setting circuit 14. 45...8-bit comparison circuit, 46...ROM,
47... Address counter, 48... Shift register, 49... Decoder, 50... OR gate. FIG. 10: A diagram of a specific example of the decoder 49.

Claims (1)

[Claims] 1. A main oscillator, a sub oscillator, a beat signal generating means for generating a beat signal from the oscillation output of the main oscillator and the sub oscillator, a counting means for generating a count proportional to the beat signal at a specific period, and the count. Boundary value setting means for arbitrarily setting a number boundary and outputting a plurality of boundary values, and comparing the frequency from the main oscillator and the frequency from the sub oscillator to compare the height of the ambient temperature with respect to the oscillator peak temperature. frequency comparing means for outputting the comparison result, comparing the count number from the counting means and the boundary value from the boundary value setting means, selecting the boundary value closest to the count number; The ambient temperature is specified based on the boundary value and the comparison result from the frequency comparison means, and a comparator outputs a digital value corresponding to the specified temperature, and counts clock pulses during a specific scanning cycle period of the liquid crystal display driver. ,
a preset counter that is preset by a digital value from the comparator to determine the initial value of the clock pulse count; a flip-flop that is reset by the output of the preset counter and is set in synchronization with the start of the scan cycle; A liquid crystal display device comprising: a liquid crystal drive circuit which controls a pulse width by an output from the flip-flop, and drives a liquid crystal display by the controlled pulse width.