JPS6384167A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS6384167A JPS6384167A JP61230387A JP23038786A JPS6384167A JP S6384167 A JPS6384167 A JP S6384167A JP 61230387 A JP61230387 A JP 61230387A JP 23038786 A JP23038786 A JP 23038786A JP S6384167 A JPS6384167 A JP S6384167A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- phosphorus
- diffusion layers
- film
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 17
- 239000011574 phosphorus Substances 0.000 claims abstract description 17
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- -1 phosphorus ions Chemical class 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 210000004027 cell Anatomy 0.000 description 12
- 230000005684 electric field Effects 0.000 description 5
- 230000005641 tunneling Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 102100037807 GATOR complex protein MIOS Human genes 0.000 description 1
- 101000950705 Homo sapiens GATOR complex protein MIOS Proteins 0.000 description 1
- 229910017997 MIO3 Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910000473 manganese(VI) oxide Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はＭＩＯ８（金属−絶縁物−酸化シリコン膜−半
導体）構造の電界効果トランジスタからなる不揮発性メ
モリトランジスタと、そのメモリトランジスタを選択す
るための電界効果トランジスタとから構成された半導体
記憶装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a nonvolatile memory transistor consisting of a field effect transistor with an MIO8 (metal-insulator-silicon oxide film-semiconductor) structure, and an electric field for selecting the memory transistor. The present invention relates to a semiconductor memory device composed of an effect transistor.
従来の技術
ＭＩＯＳ型不揮型性揮発性メモリトランジスタート−基
板間に２０〜３０Ｖ程度の高電圧を印加し、酸化シリコ
ン膜と絶縁膜の界面、またはその近傍の絶縁膜中のトラ
ップ準位に、半導体側から電荷の注入、蓄積を行ない、
トランジスタのしきい値電圧を変化させて情報を記憶さ
せるものである。Conventional technology A high voltage of about 20 to 30 V is applied between the MIOS type non-volatile volatile memory transistor and the substrate to trap levels in the insulating film at or near the interface between the silicon oxide film and the insulating film. , injects and accumulates charge from the semiconductor side,
Information is stored by changing the threshold voltage of a transistor.
従来、ＭＩＯ８ＩＯ８型不揮発性メモリトランジスタ的
なものとして、ＭＮＯＳ（金属−窒化シリコン膜−酸化
シリコン膜−半導体）構造の不揮発性メモリトランジス
タがよ（知られているが、このＭ Ｎ ＯＳメモリトラ
ンジスタを用いた半導体集積回路では、ＭＮＯＳメモリ
トランジスタ以外に、そのメモリトランジスタを選択す
るための電界効果型トランジスタを共存させる必要があ
り、したがって、従来半導体記憶装置のセルは、第２図
に示すような断面構造が用いられている。Conventionally, a nonvolatile memory transistor of the MNOS (metal-silicon nitride film-silicon oxide film-semiconductor) structure has been used as a type of MIO8IO8 type nonvolatile memory transistor. In conventional semiconductor integrated circuits, in addition to MNOS memory transistors, it is necessary to coexist a field effect transistor for selecting the memory transistor. Therefore, the cells of conventional semiconductor memory devices have a cross-sectional structure as shown in FIG. is used.
同図中、１はＰ型シリコン基板、１３．１４゜１５はｎ
型拡散層、９はトンネリング媒体となりうる薄い酸化シ
リコン膜、１１は窒化シリコン膜、８および１２はポリ
シリコン膜からなるゲート電極、７はスイッチングトラ
ンジスタのゲート絶縁膜としての酸化シリコン膜である
。In the figure, 1 is a P-type silicon substrate, 13.14°15 is n
A type diffusion layer 9 is a thin silicon oxide film that can serve as a tunneling medium, 11 is a silicon nitride film, 8 and 12 are gate electrodes made of polysilicon films, and 7 is a silicon oxide film as a gate insulating film of a switching transistor.
発明が解決しようとする問題点
第２図に示すような従来のメモリセル構造においては、
ＭＮＯＳメモリトランジスタとＭＯＳトランジスタから
なる２トランジスタ構成であり、メモリゲートと選択ゲ
ートが離れて形成されており、高集積化しに（い構造と
なっている。また、ＭＮＯＳメモリトランジスタはソー
スおよびドレイン領域間にはさまれたチャネル領域に対
向する部分全体に極薄の酸化シリコン膜９が広がってお
り、さらに、この極薄の酸化シリコン膜９に接して、上
部に２０〜３０Ｖの電圧で十分書き込み、消去を行うこ
とができるように比較的薄く窒化シリコン膜１１を−様
な厚さに形成している。したがって、情報書き込み時に
ゲートをｏｖとし、ドレインに２０〜３０Ｖの高電圧を
印加した際に、ゲート電極−トレイン間の電界がドレイ
ン−基板間の電界に大きく影響を与え、ドレイン近傍の
チャネル領域で電界集中が起こり、ドレイン−基板間の
ブレークダウンを生じたり、その領域上の極薄酸化シリ
コン膜部分が破壊しやすいという欠点を有しており、回
路設計上の一つの障害になっていた。Problems to be Solved by the Invention In the conventional memory cell structure as shown in FIG.
It has a two-transistor configuration consisting of an MNOS memory transistor and a MOS transistor, and the memory gate and selection gate are formed separately, making it an easy structure for high integration. An ultra-thin silicon oxide film 9 is spread over the entire portion facing the channel region sandwiched between the two, and in contact with this ultra-thin silicon oxide film 9, sufficient writing is performed on the upper part with a voltage of 20 to 30V. The silicon nitride film 11 is formed to a relatively thin thickness such that it can be erased.Therefore, when writing information, when the gate is set to OV and a high voltage of 20 to 30 V is applied to the drain, , the electric field between the gate electrode and the train greatly affects the electric field between the drain and the substrate, and electric field concentration occurs in the channel region near the drain, resulting in breakdown between the drain and the substrate and ultra-thin oxidation on that region. It has the disadvantage that the silicon film part is easily destroyed, which has been an obstacle in circuit design.
本発明は、かかる問題に鑑み、ＭＩＯ３型不揮発性メモ
リトランジスタと、そのメモリトランジスタを選択する
電界効果トランジスタから構成されるメモリセル構造に
おいて、その高耐圧化と同時に、セル面精の大幅な縮少
をはかることのできる構造を提供することにある。In view of such problems, the present invention aims to significantly reduce the cell surface precision while increasing the withstand voltage in a memory cell structure consisting of an MIO3 type nonvolatile memory transistor and a field effect transistor that selects the memory transistor. The goal is to provide a structure that can measure the
問題点を解決するための手段
上記目的を達成するために、本発明は一導電型半導体基
板の表面領域に互いに離れて設けられた反対導電型の第
１．第２および第３の拡散層を備え、前記第１と第２の
拡散層にはさまれた第１のチャネル領域上に第１の絶縁
膜により離隔された第１のゲート電極を備え、前記第２
．第３の拡散層にはさまれた第２のチャネル領域上に第
２および第３の絶縁膜積層により離隔された第２のゲー
ト電極を備えた半導体記憶装置において、前記第１およ
び第３の拡散層が２種類の不純物により形成された拡散
層からなり、前記第２の拡散層が１種類の不純物により
形成された拡散層からなる半導体記憶装置であり、必要
に応じ、前記第１のゲート電極と第２のゲート電極がオ
ーバーラツプさせること、上記第２のチャネル領域の両
端部分に対向した第２の絶縁膜の膜厚が、上記第２のチ
ャネル領域の中央部分より厚（することができるもので
ある。Means for Solving the Problems In order to achieve the above object, the present invention provides first semiconductor substrates of opposite conductivity type provided on the surface region of a semiconductor substrate of one conductivity type and spaced apart from each other. comprising second and third diffusion layers, a first gate electrode separated by a first insulating film on a first channel region sandwiched between the first and second diffusion layers; Second
．． In a semiconductor memory device, a second gate electrode is provided on a second channel region sandwiched between a third diffusion layer and separated by a second and third insulating film stack. The semiconductor memory device is a semiconductor memory device in which the diffusion layer is formed of two types of impurities, and the second diffusion layer is formed of one type of impurity, and if necessary, the first gate The electrode and the second gate electrode may overlap, and the second insulating film facing both end portions of the second channel region may be thicker than the center portion of the second channel region. It is something.
作用
本発明のメモリセル構造によれば、第１および第３の拡
散層が２種類の不純物による２重拡散層から構成され、
さらに第２のチャネル領域の両端部分に対向した第２の
絶縁膜の膜厚が、上記第２のチャネル領域の中央部分の
それより厚いため、メモリトランジスタのドレイン近傍
のチャネル領域での電界集中を緩和することが可能とな
る。さらに第１と第２のゲート電極をオーバーラツプさ
せることにより、メモリセルの高積化が可能となる。な
お、前記オーバーラツプした部分がオフセットとならな
いように、第１と第２のチャネル領域の間に第２の拡散
層を設けた構造としている。Operation According to the memory cell structure of the present invention, the first and third diffusion layers are composed of double diffusion layers made of two types of impurities,
Furthermore, since the thickness of the second insulating film facing both end portions of the second channel region is thicker than that of the central portion of the second channel region, electric field concentration in the channel region near the drain of the memory transistor is reduced. It becomes possible to relax. Furthermore, by overlapping the first and second gate electrodes, it becomes possible to increase the stacking capacity of the memory cells. Note that a second diffusion layer is provided between the first and second channel regions so that the overlapping portions do not become offset.
実施例 以下、具体的な実施例を図面を用いて説明する。Example Hereinafter, specific examples will be described using the drawings.
第１図は本発明の一実施例であるメモリセルの断面構造
を示す図である。図において１はＰ型シリコン基板、２
および５はリンによるｎ型拡散層、３および６はヒ素に
よるｎ型拡散層、４はリンによるｎ型拡散層、９はトン
ネリング媒体となりうる薄い酸化シリコン膜、７および
１０は酸化シリコン膜、１１は窒化シリコン膜、８およ
び１２はポリシリコン膜からなるゲート電極である。FIG. 1 is a diagram showing a cross-sectional structure of a memory cell according to an embodiment of the present invention. In the figure, 1 is a P-type silicon substrate, 2
5 is an n-type diffusion layer made of phosphorus, 3 and 6 are n-type diffusion layers made of arsenic, 4 is an n-type diffusion layer made of phosphorus, 9 is a thin silicon oxide film that can be used as a tunneling medium, 7 and 10 are silicon oxide films, 11 is a silicon nitride film, and 8 and 12 are gate electrodes made of polysilicon films.
まず、メモリ選択用ＭｏＳトランジスタのゲート絶縁膜
となる酸化シリコン膜７を通常の熱酸化法により形成し
、酸化シリコン膜７上にリンをドープ（１０”ｃ＋＋＋
−３程度）したポリシリコン膜からなる第１のゲート電
極８を形成する。本実施例では酸化シリコン膜７の膜厚
を５００Ａ、ポリシリコン膜８の膜厚を５００ＯＡとし
た。First, a silicon oxide film 7, which will become a gate insulating film of a memory selection MoS transistor, is formed by a normal thermal oxidation method, and the silicon oxide film 7 is doped with phosphorus (10"c+++
A first gate electrode 8 made of a polysilicon film having a thickness of about -3) is formed. In this example, the thickness of the silicon oxide film 7 was 500 Å, and the thickness of the polysilicon film 8 was 500 OA.
次に、トンネリング媒体となりうる薄い酸化シリコン膜
９は、シリコン基板の酸化により形成した。トンネリン
グ効果を有効に利用するには、酸化シリコン膜９の厚さ
は１０〜３０Ａにする必要があり、本実施例では２ＯＡ
とした。また、ＭＮＯＳメモリトランジスタのチャネル
領域の両端部の厚い酸化シリコン膜１０は、膜厚を５０
０人とした。また、ＭＯＳトランジスタのチャネル領域
と、ＭＮＯＳメモリトランジスタのチャネル領域の間に
ｎ型の拡散層４を形成するが、本実施例では酸化シリコ
ン膜９，１０を形成する前にリンイオンを注入（１００
ｋｅｖ、 １ｘｌＯｅｌｌ ）することにより形成し
た。Next, a thin silicon oxide film 9 that can serve as a tunneling medium was formed by oxidizing the silicon substrate. In order to effectively utilize the tunneling effect, the thickness of the silicon oxide film 9 needs to be 10 to 30A, and in this example, the thickness is 2OA.
And so. Further, the thick silicon oxide film 10 at both ends of the channel region of the MNOS memory transistor has a thickness of 50 mm.
The number was set to 0. Further, an n-type diffusion layer 4 is formed between the channel region of the MOS transistor and the channel region of the MNOS memory transistor, but in this embodiment, phosphorus ions are implanted (100%
kev, 1xlOell).
次に、酸化シリコン膜９および同１０上の窒化シリコン
膜１１は、ＮＨ３／５ｉＨ４＝１００゜７５０℃の条件
下の気相成長法により、約５００Ａ形成させた。Next, a silicon nitride film 11 on the silicon oxide film 9 and the silicon nitride film 10 was formed to have a thickness of about 500 Å by vapor phase growth under conditions of NH3/5iH4=100.degree. and 750.degree.
次いで、窒化シリコン膜１１上にリンをドープ（１０ｃ
＋ａ 程度）したポリシリコン膜からなる第２のゲー
ト電極１２を、第１のゲート電極８とオーバーラツプさ
せるように形成する。Next, the silicon nitride film 11 is doped with phosphorus (10c).
A second gate electrode 12 made of a polysilicon film having a thickness of approximately +a is formed so as to overlap with the first gate electrode 8.
最後に、ゲート電極をマスクとしたセルファライン技術
により、まずリンイオンを打ち込み（８０ｋｅｖ、
Ｉ Ｘ １０”ｃ＋ａ−２） 、リンによるｎ型拡散層
２，５を形成し、次いでリンによるｎ型拡散層２．５の
上からヒ素イオンを打ち込み（４０ｋｅｖ ｒ ４ ×
１０ ”ｃｍ−２） 、ヒ素によるｎ型拡散層３，６を
形成して、ヒ素およびリンによる２重拡散層を形成した
。Finally, using the self-line technology using the gate electrode as a mask, phosphorus ions were first implanted (80keV,
I x 10"c+a-2), form n-type diffusion layers 2 and 5 made of phosphorus, and then implant arsenic ions from above the n-type diffusion layers 2.5 made of phosphorus (40 kev r 4 x
10''cm-2), n-type diffusion layers 3 and 6 made of arsenic were formed to form a double diffusion layer made of arsenic and phosphorus.
このＭＮＯ３型不揮発性メモリセルのドレイン耐圧は、
従来構造のドレイン耐圧（〜１５ｖ）に比べ５〜１０ｖ
耐圧を向上させることが可能であり、さらにメモリ選択
用ＭＯＳトランジスタのゲート電極とＭＮＯＳメモリト
ランジスタのゲート電極がオーバーラツプできるような
構造としているため、メモリセルの高集積化が可能とな
る。The drain breakdown voltage of this MNO3 type nonvolatile memory cell is
5-10V compared to the drain breakdown voltage of conventional structure (~15V)
It is possible to improve the breakdown voltage, and since the structure is such that the gate electrode of the memory selection MOS transistor and the gate electrode of the MNOS memory transistor can overlap, it is possible to highly integrate the memory cells.
発明の詳細
な説明したところから明らかなように、本発明の構造に
よれば、メモリセルの高耐圧化と同時に、セル面積の大
幅な縮少をはかることができ、大容量メモリに適用する
際の実用上の問題解決に太き（寄与するものである。As is clear from the detailed description of the invention, according to the structure of the present invention, it is possible to increase the breakdown voltage of the memory cell and at the same time significantly reduce the cell area. This will greatly contribute to solving practical problems.
第１図は本発明の一実施例を説明するための構造断面図
、第２図は従来のＭＮＯ８型不揮発性メモリセルの構造
断面図である。
１・・・・・・Ｐ型シリコン基板、２．４．５・・・・
・・リンによるｎ型拡散層、３，６・・・・・・ヒ素に
よるｎ型拡散層、７，１０・・・・・・厚い酸化シリコ
ン膜、９・・・・・・薄い酸化シリコン膜、１１・・・
・・・窒化シリコン膜、８．１２・・・・・・ゲート電
極。FIG. 1 is a structural sectional view for explaining one embodiment of the present invention, and FIG. 2 is a structural sectional view of a conventional MNO8 type nonvolatile memory cell. 1...P-type silicon substrate, 2.4.5...
...N-type diffusion layer made of phosphorus, 3,6...N-type diffusion layer made of arsenic, 7,10...Thick silicon oxide film, 9...Thin silicon oxide film , 11...
...Silicon nitride film, 8.12...Gate electrode.
Claims (4)
けられた前記基板と反対導電型の第１、第２および第３
の拡散層を備え、前記第１と第２の拡散層にはさまれた
第１のチャネル領域上に第１の絶縁膜により離隔された
第１のゲート電極を備え、前記第２、第３の拡散層には
さまれた第２のチャネル領域上に第２および第３の絶縁
膜積層により離隔された第２のゲート電極を備えた半導
体記憶装置において、前記第１および第３の拡散層が２
種類の不純物により形成された拡散層からなり、前記第
２の拡散層が１種類の不純物により形成された拡散層か
らなることを特徴とする半導体記憶装置。(1) First, second, and third semiconductor substrates of a conductivity type opposite to that of the substrate, provided in a surface region of a semiconductor substrate of one conductivity type and separated from each other.
a first gate electrode separated by a first insulating film on a first channel region sandwiched between the first and second diffusion layers; In the semiconductor memory device, a second gate electrode is provided on a second channel region sandwiched between diffusion layers, and is separated by a second and third insulating film stack. is 2
1. A semiconductor memory device comprising a diffusion layer formed of different types of impurities, and wherein the second diffusion layer is formed of a diffusion layer formed of one type of impurity.
リンであることを特徴とする特許請求の範囲第（１）項
記載の半導体記憶装置。(2) The semiconductor memory device according to claim (1), wherein the two types of impurities are phosphorus and arsenic, and the one type of impurity is phosphorus.
縁膜が窒化シリコン膜であることを特徴とする特許請求
の範囲第（１）項または第（２）項記載の半導体記憶装
置。(3) The semiconductor according to claim (1) or (2), wherein the first and second insulating films are silicon oxide films and the third insulating film is silicon nitride film. Storage device.
ラップするように形成されたことを特徴とする特許請求
の範囲第（１）項記載の半導体記憶装置。(4) The semiconductor memory device according to claim (1), wherein the first gate electrode and the second gate electrode are formed to overlap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61230387A JPH0758741B2 (en) | 1986-09-29 | 1986-09-29 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61230387A JPH0758741B2 (en) | 1986-09-29 | 1986-09-29 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6384167A true JPS6384167A (en) | 1988-04-14 |
| JPH0758741B2 JPH0758741B2 (en) | 1995-06-21 |
Family
ID=16907076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61230387A Expired - Lifetime JPH0758741B2 (en) | 1986-09-29 | 1986-09-29 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758741B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100309815B1 (en) * | 1998-03-26 | 2001-11-15 | 박종섭 | Structure of split gate type flash EEPROM cell and method of operating the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5780779A (en) * | 1980-11-07 | 1982-05-20 | Fujitsu Ltd | Semiconductor non-volatile memory |
| JPS58158964A (en) * | 1982-02-25 | 1983-09-21 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Semiconductor device and method of producing same |
| JPS60124965A (en) * | 1983-12-10 | 1985-07-04 | Matsushita Electronics Corp | Manufacture of semiconductor device |
-
1986
- 1986-09-29 JP JP61230387A patent/JPH0758741B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5780779A (en) * | 1980-11-07 | 1982-05-20 | Fujitsu Ltd | Semiconductor non-volatile memory |
| JPS58158964A (en) * | 1982-02-25 | 1983-09-21 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Semiconductor device and method of producing same |
| JPS60124965A (en) * | 1983-12-10 | 1985-07-04 | Matsushita Electronics Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100309815B1 (en) * | 1998-03-26 | 2001-11-15 | 박종섭 | Structure of split gate type flash EEPROM cell and method of operating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0758741B2 (en) | 1995-06-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |