JPS6383992U - - Google Patents
Info
- Publication number
- JPS6383992U JPS6383992U JP17899886U JP17899886U JPS6383992U JP S6383992 U JPS6383992 U JP S6383992U JP 17899886 U JP17899886 U JP 17899886U JP 17899886 U JP17899886 U JP 17899886U JP S6383992 U JPS6383992 U JP S6383992U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- inverter
- pulse train
- output
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 1
Description
第１図はこの考案の一実施例の構成を示す回路
図、第２図は出力トランジスタのコレクタ遮断電
流による作動を説明するための要部回路図、第３
図は発振器の両制御発振出力端からそれぞれ出力
されるパルス列制御信号の波形図である。
Ｔ１〜Ｔ４……出力トランジスタ、Ｔｓ１〜Ｔ
ｓ４……制御用トランジスタ、５……レギユレー
タ（直流電源）、８……発振器（チヨツパ制御手
段）。
Fig. 1 is a circuit diagram showing the configuration of an embodiment of this invention, Fig. 2 is a main part circuit diagram for explaining the operation by the collector cut-off current of the output transistor, and Fig. 3 is a circuit diagram showing the configuration of an embodiment of this invention.
The figure is a waveform diagram of pulse train control signals output from both controlled oscillation output terminals of the oscillator. T 1 to T 4 ...output transistor, Ts 1 to T
s4 ... Control transistor, 5... Regulator (DC power supply), 8... Oscillator (chopper control means).
Claims (1)
ジ接続された上段及び下段の各一対の出力トラン
ジスタのうち正常作動時にコレクタ電流方向がそ
れぞれ共通となる二組の上段及び下段の両出力ト
ランジスタを、二つの異なる連続的なパルス列制
御信号を出力するチヨツパ制御手段を介してそれ
ぞれ所定のパルス列毎に交互にオン、オフ状態に
することによつてインバータ動作が行なわれるト
ランジスタインバータにおいて、前記各出力トラ
ンジスタのベースとエミツタとの間に接続される
と共に、一方の組の出力トランジスタが前記制御
信号のオン信号を受けて他方の組の出力トランジ
スタをオフ状態にすべくオン状態となる制御用ト
ランジスタを設けたことを特徴とするトランジス
タインバータ。 Two pairs of upper and lower output transistors, each of which has a common collector current direction during normal operation, are connected between the DC power supply lines and are bridge-connected. In a transistor inverter in which an inverter operation is performed by alternately turning on and off states for each predetermined pulse train through a chopper control means that outputs different continuous pulse train control signals, the base of each of the output transistors and A control transistor is provided which is connected between the emitter and the output transistor of one set and turns on in response to the on signal of the control signal to turn the output transistor of the other set into the off state. Characteristic transistor inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17899886U JPS6383992U (en) | 1986-11-20 | 1986-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17899886U JPS6383992U (en) | 1986-11-20 | 1986-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6383992U true JPS6383992U (en) | 1988-06-01 |
Family
ID=31121656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17899886U Pending JPS6383992U (en) | 1986-11-20 | 1986-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6383992U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5561282A (en) * | 1978-10-27 | 1980-05-08 | Nippon Soken Inc | Separate excitation type inverter circuit |
-
1986
- 1986-11-20 JP JP17899886U patent/JPS6383992U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5561282A (en) * | 1978-10-27 | 1980-05-08 | Nippon Soken Inc | Separate excitation type inverter circuit |