JPS6382515A - Adder - Google Patents

Abstract

PURPOSE:To execute an addition operation at high speed by providing a first transfer means for transferring the carry from all adders of low order digit to all adders of high order digit when there is no carry from all the adders and disconnecting both means when the carry is transferred through a specific second transfer means parallel therewith. CONSTITUTION:A clock inverter 13 constitutes a skip circuit 11 of a NAND gate 7 and an inverter 15, the inverter 13 is conducted and controlled by a clock signal phi and its inverted clock signal phi and the output of the gate 7 having the input of the arithmetic result P0-P3 of all the adders 1 is defined to be the inverted clock signal phi. Further, the output of the inverter 15 having the output to be an input is defined to be the clock signal phi, a clock inverter 21 is connected between the outputs of a bus transistor 3 and the inverter 13 conducted and controlled by the result P3, the output of the gate 7 is defined to be the clock signal phi and the output of the inverter 15 is defined to be the inverted clock signal phi, respectively to conduct and control the inverter 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an adder that can achieve high-speed addition operations with a relatively simple circuit configuration.

(Prior art) The conventionally known Manchester type phase-up adder is
The adder is realized with a relatively simple configuration by generating a carry (carry signal) or transmitting a carry from a lower digit for each full adder.

FIG. 5 is a block diagram of a Manchester type phase-up adder (hereinafter simply referred to as an "adder"). The Manchester-type phase-up adder shown in the figure has four bits from the Oth bit to the 3rd bit.
Only the part that performs bit addition is extracted. In this adder, when addition information A and B are given to each full adder 1 connected in series, each full adder performs the addition, and obtains the sum S of the addition information as the addition result. Furthermore, a carry accompanying the addition is generated and sent to the higher order digit, or a carry is not generated and the carry from the lower order digit is transmitted.

The generation and transmission of this carry is the addition information △.

8 (177). This is determined by the full adder 1 performing an exclusive OR operation (AΦB) of the addition information A and B,
If the operation result is P, then P is 0'', that is, A=B, and when A=8="1", carry is "1'°, and when A-B-"0", carry is Generate it Ops and send it to the upper digits.

On the other hand, when P is 1'', that is, A4B, no carry is generated and the carry from the lower digit is transmitted to the upper digit.

This carry transmission is carried out between a P-channel MO8 type transistor (hereinafter referred to as rPMO3J) and an N-channel MO8 type transistor (hereinafter referred to as rNM
The upper digit full adder 1 is connected to the upper digit through a pass transistor 3 (referred to as O8J) and an inverter 4 for waveform shaping.
given to. Therefore, the carry transfer time depends on the on-resistance R of PMO8 and NMO8 constituting the pass transistor 3 and the capacity of each terminal, and as the number of pass transistors 3 connected in series increases, Delay increases.

In order to reduce this delay, the pass transistor 3 is divided into blocks and a skip circuit 5 is provided for each block.In the adder shown in FIG. The bit-th full adder 1 is one block, and this block has one skip circuit 5.
is provided.

The skip circuit 5 uses four pass transistors 3 when no carry occurs in all the full adders 1 from the Oth bit to the third bit and the carry transmitted from the lower digit is transmitted to the upper digit. It conveys a skip and a carry. That is, the NAND gate 7 detects that Po to P3 are all "1", and according to this detection result, PMO8 and N
The four pass transistors 3 connected in series and the skip transistor 9 connected in parallel are controlled to be conductive, and a carry is transmitted through the skip transistor 9. When no carry occurs in all the full adders 1 at the 0th bit to the 3rd bit and Po=P:+ becomes 1'', the output of the NAND gate 7 becomes II 111,
Skip transistor 9 becomes conductive and carry is transmitted.

In this way, by providing the skip circuit 5 to skip carries, when a carry is not generated from all the full adders 1 of one block, the carry transmitted from the lower digit to the upper digit is serially transmitted. The signal is transmitted at a higher speed than the case where the signal is transmitted through the four pass transistors 3 connected to the gate.

(Problems to be Solved by the Invention) As explained above, by providing the skip circuit 5, carry transmission can be performed at high speed.

However, when the skip transistor 9 of the skip circuit 5 is in a conductive state and skips a carry, all four pass transistors 3 are also in a conductive state because PO to P3 are 1''. , as shown in FIG. 6, each on-resistance R and each capacitance IC of the pass transistor 3 become a load on the skip transistor 9 via the wired-OR connected point A, causing a delay in carry transmission. .

For example, when point A is at the “1” level, carry 110
When IT is skipped, the carry reaches point A faster from the transmission path of the skip transistor 9 than from the transmission path of each pass transistor 3 connected in series. At this time, if the potential of each capacitance of each pass transistor 3 is at the "1" level, the carry "O pass" transmitted to point A via the skip transistor 9,
A portion of the charge stored in each capacitance of each pass transistor 3 is discharged. For this reason, as shown in FIG. 7, the fall of the potential at point A is delayed, and the transmission of carry "0" is delayed. Also, carry 111!+
Similarly, in the case of skipping A, as shown in FIG.
The rise of the potential at the point is delayed, and the transmission of carry 1°' is delayed. On the other hand, when the carry level and the eight levels of each pass transistor 3 are at the same level, the carry transmission becomes faster.

In this way, when a carry is skipped, each pass transistor 3 becomes a load on the skip transistor 9, so the transmission speed of the carry depends on the capacity state of each pass transistor 3, and the carry is transmitted. If the level of the carry differs from the level of the capacitance of each pass transistor 3, the transmission of the carry is delayed, which is an obstacle to increasing the calculation speed of the adder.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and an object of the present invention is to provide an adder that can transmit carries at high speed and perform addition operations at even higher speeds.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a plurality of full adders that generate carries based on addition information to be added, and a plurality of full adders that generate carries based on addition information to be added. a first transmitting means for transmitting a carry generated from a lower digit full adder to a next higher digit full adder of the lower digit full adder when a carry does not occur from the first transmitter;
a second transmitting means that is provided in parallel with the first transmitting means with respect to the carry transmitting direction and transmits the carry generated from the lower digit full adder by a predetermined number of digits to the upper digit full adder; and means for disconnecting the first transmitting means and the second transmitting means when the carry is transmitted to the full adder of the upper digit through the second transmitting means.

(Operation) In the adder of the present invention, when the carry generated from the full adder for lower digits is skipped by a predetermined number of digits via the second transmission means and transmitted to the full adder for upper digits, , the first transmission means and the second transmission means are disconnected.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a Manchester type phase-up adder according to an embodiment of the present invention. Components with the same reference numerals as in FIG. 5 have the same functions, and their explanation will be omitted.

When skipping a carry, the adder shown in FIG. 1 separates the carry transmission path via four pass transistors 3 connected in series from the skip transmission path, The skip circuit 11 becomes
This reduces the load on the vehicle.

The skip circuit 11 has a clocked inverter 13 and an NA
It is composed of an ND gate 7 and an inverter 15.

The conduction of the clocked inverter is controlled by a clock signal φ and an inverted clock signal φ, which is an inverted signal of the clock signal φ.
The clock signal φ operates in the same way as a normal inverter, and the clock signal φ is at the 0 level, and the inverted clock signal φ is at the 1 degree level.
At 'level', it becomes a high impedance state regardless of the level of the input signal.

This locked inverter is PMO817a,
17b, NMO819a, and 19b is shown in FIG. The clocked inverter not shown in Figure 2 is
PMO3 whose gate terminal is given an inverted clock signal φ
17a, and PMO8 whose gate terminal receives an input signal.
17b are connected in series between the voltage source Vcc and the output OUT, and an input signal is given to the gate terminal of the NMO819.
a, and N to which the inverted clock signal φ is applied to the gate terminal.
MO819b is connected between the output 01JT and the ground.

In such a configuration, the clock signal φ is
I! When the inverted clock signal φ reaches the "o" level, the PMO 817a and the NMO 819b become conductive, and a signal obtained by inverting the input signal applied to the input fN is sent to the output OUT.

On the other hand, when the clock signal φ becomes the "0" level and the inverted clock signal φ becomes the II 1 I+ level, the PMO8
17a and NMO319b become non-conductive, and the output O
The UT is in a high impedance state regardless of the level of the input signal.

Returning to FIG. 1, as described above, the locked inverter 13 receives the carry sent from the lower digit to its input, and its output is the carry power of the upper digit, and is in a conductive state at the time of skipping. The carry generated from the lower digits is transmitted to the higher digits.

The inverted clock signal φ of the clocked inverter 13 is P
The clock signal φ is the output of the NAND gate 7p which receives the inputs from o to P3, and the clock signal φ is the output of the inverter 15 which receives the output of the NANO gate.

Further, a clocked inverter 21 is connected between the pass transistor 3 whose conduction is controlled by P3 of the third bit full adder and the output of the clocked inverter 13, and this clocked inverter 21 is connected to the NAND gate 7
The output of the inverter 15 is used as a clock signal, and the output of the inverter 15 is used as an inverted clock signal φ to control conduction. However, since the clocked inverter 13 and the clocked inverter 21 are controlled to be conductive by the contradictory clock signal φ and the inverted clock signal φ, when one clocked inverter is in a conductive state, the other clocked inverter is in a conductive state. is in a non-conducting state.

Therefore, the clocked inverter 21 operates from PO to P3.
becomes non-conductive when all becomes "1" and enters the skip state, and the carry transmission path when a carry occurs in full adder 1 and the transmission path during skip are separated, and the path connected in series during skip is separated. The resistance and capacitance of the transistor 3 are kept from becoming a load on the clocked inverter 13.

As explained above, this embodiment is constructed, and the operation of this embodiment will be explained next.

First, a case where carries from lower digits are skipped will be explained. For each full adder 1, A
O≠Bo, At≠8+, A2≠82, A3≠83
When the addition information A and B are given, the full adder 1 performs an exclusive OR operation A and B of the respective addition information. Po=P3, which is the result of this operation, is all "1", and no carry is generated in all the full adders 1.

As a result, all pass transistors 3 become conductive. Further, the output of the NAND gate becomes 0'', and the output of the inverter 15 becomes 1''. Therefore, the 1" level clock signal .phi. and the "0" level inverted clock signal .phi. are supplied to the clocked inverter 13, and the clocked inverter 13 becomes conductive. Further, the clock signal φ at the '0' level and the inverted clock signal φ at the '1' level are supplied to the clocked inverter 21, and the clocked inverter 21 becomes non-conductive.

As a result, even though all the pass transistors 3 are in a conductive state, the pass transistor 3 whose conduction is controlled by P3 and the output of the clocked inverter 13 are in a disconnected state, so that the data is transmitted from the lower digits. The carry is transmitted to the higher order digits via the clocked inverter 13.

Next, a case will be described in which carries from lower digits are not skipped.

When at least one full adder 1 is given addition information that becomes A-8, a carry is generated from the full adder 1 to which this addition information is given, and the P output of this full adder 1 is "O". becomes.

As a result, the pass transistor 3 whose conduction is controlled by this P becomes non-conductive. Further, the output of the NAND gate becomes "1", the clock signal φ of the clocked inverter 13 is lQ91, the inverted clock signal φ is 1", the clock signal φ of the clocked inverter 21 is "1", and the inverted clock The signal φ becomes "0", the clocked inverter 13 becomes non-conductive, and the clocked inverter 21 becomes conductive.

Therefore, the carry from the lower digit is not transmitted to the upper digit, and the carry generated from the full adder 1 is transmitted to the upper digit via the clocked inverter 21.

By the way, in this embodiment, since the carry is transmitted via the clocked inverter 13 at the time of skip,
Compared to the case of the skip transistor 9 described above, a gate delay due to the clocked inverter 13 occurs. However, in the wired-OR format shown in FIG. 5, an inverter 4 is used to shape the waveform with slow falling and rising edges by transmitting the carry to the pass transistor 3.
There was a gate delay due to Therefore, in this embodiment, compared to the wired-OR format shown in FIG. 5, carry transmission is not delayed due to gate delay.

Therefore, in the wired-OR format shown in FIG. 5, the resistance of the pass transistor 3 and each set serve as a load on the clocked inverter 13 during skipping, so the output after waveform shaping is as shown in FIG. In contrast, in this embodiment, the pass transistor 3 and the clocked inverter 13 are disconnected by the clocked inverter 21, and the pass transistor 3 is clocked at the time of skipping. Since the clocked inverter 13 does not become a load on the clocked inverter 13 and has a driving capability, as shown in FIG.
Carry will be transmitted fairly quickly.

Further, in this embodiment, the carry is skipped by four digits, but the number is not limited to this. Therefore, when a carry is skipped, the carry transmission speed is always constant regardless of the number of digits to be skipped.

[Effect of the Invention 1] As explained above, according to the present invention, the carry generated from the full adder for the lower digits is skipped by a predetermined digit via the second transmission means, and the carry is added to the full adder for the upper digits. When the transmission is transmitted to the device, the first transmission means and the second transmission means are disconnected, so that the first transmission means does not become a load on the second transmission means, and the second transmission means The load can be reduced. As a result, carry transmission during skipping is performed at high speed, and addition operations can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an adder according to an embodiment of the present invention, FIG. 2 is a configuration diagram showing an example of an integral part of the clocked inverter shown in FIG. 1, and FIG. 3 is a carry transmission speed in FIG. 5. FIG. 4 is a diagram showing the carry transmission speed in FIG. 1, FIG. 5 is a block diagram showing an example of a conventional adder, and FIG. The illustrated figure, FIG. 7, is a diagram showing the carry transmission speed in FIG. 6. (Explanation of symbols representing main parts of the diagram) 1...Full adder 3...Pass transistor 13.21...Clocked inverter upper side 1 Figure 21! ! 1 4t Ri single power Figure 5

Claims (1)

[Claims] Multiple full adders generate carries depending on the addition information to be added, and if a carry does not occur from this full adder, the carry generated from the full adder of the lower digit is transferred to the next higher order of this full adder. The first to be transmitted to the full adder of digits
a transmission means, which is provided in parallel with the first transmission means with respect to the carry transmission direction, and transmits the carry generated from the lower digit full adder by a predetermined number of digits to the upper digit full adder. a second transmitting means, and when the carry is transmitted to the full adder of the upper digit through the second transmitting means, the first
An adder comprising means for disconnecting the transmission means and the second transmission means.