JPS6380371A - Coordinate transforming device - Google Patents

Abstract

PURPOSE:To eliminate the unnecessary latency time of each coordinate unit to efficiently perform the coordinate transform operation by running the same software with a primary delay in each coordinate transform unit. CONSTITUTION:In a distributing unit 1, coordinate data temporarily stored in a FIFO memory 11 is delayed by one clock and is successively stored in FIFO memories 21, 31, 41, and 51 of coordinate transform units 2, 3, 5, and matrix element data read out from a matrix stack 8 is delayed by one clock and is successively stored in FIFO memories 21, 31, 41, and 51. The same control data is delayed by one clock and is supplied to units 2...5 by a control unit and a timing control unit. The same accumulating operation is successively performed with one clock delay on the basis of data stored in FIFO memories 21-51, and the accumulation result is successively obtained with one clock delay.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a coordinate conversion device, and more specifically,
The present invention relates to a coordinate conversion device used in a graphic display device, etc.

<Prior Art> Conventionally, in graphic display devices, it has been common practice to display figures by rotating them, enlarging them, or reducing them. and,
As mentioned above, in order to display a shape that has been subjected to various transformation processes, the basic shape data is multiplied by a matrix corresponding to the transformation process, and the figure is displayed based on the multiplication result. , enlarged, reduced, etc. figures are displayed visually.

By the way, for example, in the case of a three-dimensional figure, the above multiplication means performing matrix multiplication such as
1y+a31z+a41, y coordinate is a12x+a22
y + a32z + a42.2 coordinates are a 13x
+a23y + a33z + a43, W coordinate (coordinate for perspective) is a 14+ a 24+ a 34+ a
44.

FIG. 3 is an electrical circuit diagram showing a conventional example of a coordinate conversion device for calculating the above-mentioned converted coordinate values, and is
The original coordinate data sequentially transmitted from (121) to X register (122) and y register (123)
, and 2 registers (124), and the data from each of the above registers is sent to the multiplexer (12B).
(127) Serial input/parallel input/serial output multiplier (129) (130) via (128)
(131) and stack memory
Shift registers (132) (133) (13) supplied with data for x, y, z coordinate transformation from (125)
4) is also applied to the serial input/parallel input/serial output multiplier (129) (130
) (131), serial input/parallel input/serial output multiplier (129) (130) (131)
, and shift registers (132) (133) (1
34) performs a multiplication operation every time the system clock for multiplication is supplied to the serial input/parallel input/serial output multiplier (129), (130), and (131). The data of the shift register (IH), in which data for movement conversion is supplied from the stack memory (125), is supplied to the serial adder (135) operated by the system clock for multiplication, and the data is added from the serial adder (135). The output is supplied to a shift register (13B) to which data for W coordinate conversion from the stack memory (125>) is supplied.

Therefore, each time the system clock for multiplication is supplied, the multiplication result is obtained one bit at a time, and the serial adder (135
) and finally the shift register (13B
) can store coordinate transformation data.

Therefore, coordinate conversion data can be obtained by outputting the contents of the shift register (13B) in parallel.

In addition, in the case of matrix-matrix operations (multiplication), data from the stack memory (125) is transferred to the multiplier (129) by the multiplexer (12G) (127) (128).
(130) is supplied to (131).

<Problems to be Solved by the Invention> In the coordinate conversion device with the above configuration, a large number of system clocks depending on the data length are required until the coordinate conversion data is finally obtained. There is a problem in that it takes a long time to obtain coordinate transformation data.

In a graphic display device, since a large number of coordinate conversion processes are frequently performed, the above-mentioned problem becomes particularly noticeable, resulting in the problem that the drawing speed cannot be increased very much.

<Object of the invention> This invention was made in view of the above problems,
It is an object of the present invention to provide a coordinate conversion device that can increase the speed of coordinate conversion.

Means for Solving Problems> To achieve the above object, the coordinate conversion device of the present invention includes an input/output FIFO memory and multiplication/accumulation based on data read from the input/output FIFO memory. a plurality of sets of coordinate transformation units each having a parallel multiplication/accumulation unit for performing multiplication and accumulation, and a holding register for holding the parallel multiplication/accumulation results, and a control means for generating control data for controlling the operation of the coordinate transformation unit; It has timing control means for supplying the control data output from the control means to each coordinate transformation unit while shifting the control data by a predetermined timing.

Effects> With the coordinate conversion device having the above configuration, each coordinate conversion unit sequentially reads the graphic data stored in the input/output FIFO memory and supplies it to the parallel multiplication accumulator, thereby converting the coordinate data and Performs multiplication with matrix element data and accumulation with already performed multiplication results,
The multiplication and accumulation results can be temporarily stored in a holding register, and the contents of the holding register can be output as converted coordinate data. The coordinate data output from the holding register of each coordinate conversion unit is X coordinate data and y coordinate data, respectively.
It is divided like coordinate data.

When performing the above coordinate transformation operation, each coordinate transformation unit is supplied with control data output from the control means, and performs the multiplication and accumulation operation in a predetermined order based on this control data. Since the control data output from the control means is supplied to each coordinate transformation unit with a predetermined timing shift by the timing control means, each coordinate transformation unit is supplied with the same data with a predetermined timing shift. perform the coordinate transformation operation of
Coordinate data that has been subjected to necessary transformations can be obtained.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 1 is a block diagram showing an embodiment of the coordinate conversion device of the present invention, which distributes coordinate data transmitted from a host processor (9) and matrix element data read from a matrix stack (8). Sorting unit (1
) and four sets of coordinate transformation units (2) installed together
(3) [4] [5].

The distribution unit (1) is a FIFO that temporarily stores the coordinate data transmitted from the host processor (9).
Each coordinate conversion unit [2] (3) (4) has a memory (11) and sequentially converts coordinate data read from the FIFO memory (11) or matrix element data read from the matrix stack (8). (5
) has a data bus (12).

The above four sets of coordinate transformation units (2) (3) (4)
(5) all have the same configuration, so only the configuration of the coordinate transformation unit (2) will be explained.

The above coordinate conversion unit (a is the above distribution unit (1)
FIFO that temporarily stores data transmitted from
a memory (21), a single port multiplier/accumulator (22) that performs multiplication/accumulation by inputting data read from the FIFO memory (21);
a pipeline register (23) for temporarily storing the multiplication and accumulation results output from the matrix stack (8); has a FIFO memory (24) for transmitting data towards the lower processor I.

Note that the contents of the pipeline register (23) are stored in the FIFO memory (23) only when a series of multiplication and accumulation operations are completed.
4) and is transmitted to the single-port multiplication/accumulation unit (22) until a series of multiplication/accumulation operations are completed.

Figure 2 shows the distribution unit (1), a control unit (6) for supplying control data to the four coordinate transformation units (2), (3), (4), and (5), and a timing control unit. It is a block diagram showing the configuration of the unit (7), which includes a first microprogram sequencer (61) to which a system clock is supplied, a second microprogram sequencer (62), and first to fifth pipeline registers (85). ) (6B) (87) (88) (
89).

To explain in more detail, the second microprogram sequencer (82) and the fifth pipeline register (65) are for supplying control data to the distribution unit (1), By supplying the address data output from the second microprogram sequencer (62) to the second microprogram memory (64), the control data stored at the address is read, and the fifth pipeline Register (B9
) is supplied to the above-mentioned distribution unit (1).

The first microprogram sequencer (61) and the first to fourth pipeline registers (65) (8
B) (67) (88) is the coordinate transformation unit (2)
(3) (4) This is for supplying control data to (5), and the address data output from the first microprogram sequencer (61) is
The control data stored at the address is read by supplying the control data to the microprogram memory (63) of the above-mentioned first to fourth pipeline registers (85).
It is supplied to the coordinate transformation units (2) (3) (4) (5) through (6G) (67) and (68). Specifically, the control data output from the pipeline register (65) is supplied to the coordinate transformation unit (2), and the control data output from the pipeline register (6B) is supplied to the coordinate transformation unit (3). The control data output from the pipeline register (67) is supplied to the coordinate transformation unit (4), and the control data output from the pipeline register (68) is supplied to the coordinate transformation unit (5). .

Therefore, the control data read from the microprogram memory (63) is sequentially supplied to the coordinate transformation unit [21 (3) (4) (5) with a delay of one clock.

The coordinate transformation operation by the coordinate transformation device having the above configuration will be explained below.

In addition, in the following explanation, The explanation will be based on the coordinate transformation of .

[1] Operation of the distribution unit (1) First, read the X data from the FIFO memory (11),
The FIFO memory (2
1) Store in (31) (41) (51). Next, at a timing delayed by one clock, matrix element data a 11+ is sent from the matrix stack (8).
a lLa13. A14 is read in the order of lower bit and upper bit, and each time each matrix element data is read, the corresponding FIFO memory (21) (31) (41
) (51).

Next, read the y data from the FIFO memory (11),
The FIFO memory (2
1) Store in (31) (41) (51). Then,
Matrix element data a from the matrix stack (8) at a timing delayed by one clock 21. a
22°a23. A24 is read in the order of lower bit and upper bit, and each time each matrix element data is read, the corresponding FIFO memory (21) (31) (41) (
51).

Thereafter, Z data is stored and matrix element data a is stored in the same manner.31. a32. a33. a
34 storage, W data storage, matrix element data a
41. a 42°a43. Store a44.

(Ill) Operation of coordinate conversion unit (2) First, storage areas of 16 bits each in the pipeline register (23) PR (MM), PR (ML), PR (LM), P
The contents of R(LL) are cleared to 0, and the area ACC of the single-vote multiplication accumulator (22) is cleared to 0.

Then, the data distribution by the distribution unit (1) is carried out with the operation of the data distribution unit (1).
The data is set in the multiplier register of the single port multiplier/accumulator (22), and the lower bits all (L
) in the multiplicand register of the single-vote multiplier-accumulator (22), multiply the contents of the multiplier register by the contents of the multiplicand register, and add the contents of the area ACC to obtain the multiplication-accumulation data. Pipeline register (2
3) storage area PR (LH).

Store in PR (LL).

Hereinafter, the above series of operations will be expressed as ACC+ a 11(L) x -PR(LM), P
It is abbreviated as R(LL).

Next, the area PR (ML) of the pipeline register (23)
).

The contents stored in PR(LM) are stored in the area ACC of the single port multiplication/accumulation 2S (22) (hereinafter, this operation is abbreviated as ACC-PR(ML) and PR(LM)), and then ACC+ a 11(M) x -PR(
ML) and PR (LM) operations.

Below, ACC←PR(LM), PR(LL), ACC10a
21(L) y = PR(LM), PR(LL), A
CC←PR(ML), PR(LM), ACC+a
21(M)y-PR(ML), PR(LM), A
CC-PR(LM), PR(LL), ACC+ a
31 (L) z -1'R (LM), PR (LL),
ACC←PR(ML), PR(LM), ACC+ a
31(M) z-hPR(ML), PR(LM)
, ACC←PR(LM), PR(LL), ACC+
a 41(L) w-PR(LM), PR(LL),
ACC←PR(ML), PR(LM), ACC+ a
41(M) w 4PR(ML), PR(LM),
By performing the following operations, the calculation result of a11x+a21y+a31z+a41w can be obtained.Finally, the areas PR(ML) and PR(LM) of the pipeline register (23).

The multiplication and accumulation results stored in PR (LL) are temporarily stored in the FIFO memory (24), and the lower processor (goods)
It can be transmitted towards.

(5) Operations of coordinate transformation units (3), (4), and [5] The operations of these coordinate transformation units (3), (4), and (5) differ only in the data given; Since the operations are the same, detailed explanation will be omitted.

To summarize the above, in the distribution unit (1), FIF
The coordinate data temporarily stored in the O memory is sequentially converted into multi-coordinate transformation units (2) (3) (4) with a one-clock delay.
] (5) FIFO memory (21) (31) (4
1) The matrix element data stored in (51) and read out from the matrix stack (8) is also sequentially transferred to the FIFO memory (21) (31) (41) with a one clock delay.
) (51).

And each of the above coordinate transformation units [2] (31 (4)
(5) is supplied with the same control data by the control unit (6) and the timing control unit (7) with a one-clock delay, so the data stored in the FIFO memory as described above is Based on this, the same multiplication and accumulation operations can be performed sequentially with a one clock delay, and the multiplication and accumulation results can be obtained sequentially with a one clock delay.

Therefore, as shown in Figure 2, each coordinate transformation unit (2), (3), (4), and (5) runs the same software with a - next delay, resulting in unnecessary waiting time for each coordinate transformation unit. This makes it possible to efficiently perform coordinate conversion operations.

The above description has been made of the case where only one type of coordinate transformation such as rotation, enlargement, reduction, parallel movement, etc. is performed, but the present invention can also be applied to the case where two or more types of coordinate transformation are performed.

That is, when performing two or more types of coordinate transformation, calculations are performed between the matrices for each coordinate transformation,
All that is required is to obtain a new matrix and perform the above coordinate transformation based on the obtained matrix. Specifically, although the number of multiplication and accumulation operations will increase, it is sufficient to sequentially read the matrix element data from the two matrices to be operated on and perform the multiplication and accumulation as described above. When applying the transformation, a corresponding matrix can be obtained. Therefore, by subsequently performing coordinate transformation based on the obtained matrix and the coordinate data transmitted from the host processor (9), it is possible to obtain data that has been subjected to the desired coordinate transformation.

However, as is clear from the above explanation, in order to perform -th delay processing, each FIFO memory (11) (2
1) (31) (41) It is necessary to make the fall-through time and ready confirmation time of (51) the same (preferably close to 0), and in addition, the upper processor (9) and lower processor ( (to) requires data to be input or output in bursts.

Note that the present invention is not limited to the above-described embodiments; for example, by using a multi-vote multiplier/accumulator instead of a single-vote multiplier/accumulator, the coordinate conversion processing speed can be further increased. In addition, it is possible to make various design changes without changing the gist of the invention.

<Effects of the Invention> As described above, the present invention supplies common software to identical hardware units with a predetermined timing delay, thereby eliminating unnecessary waiting time for hardware and providing orderly and efficient software. It is possible to obtain coordinate transformation results in a single manner, and the control unit of each hardware can be shared, which has the unique effect of simplifying the configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the coordinate transformation device of the present invention, FIG. 2 is a diagram schematically showing the operation of each unit, and FIG. 3 is a block diagram showing a conventional example.

Claims (1)

[Claims] 1. FIFO memory for input/output and input/output Based on data read from FIFO memory a parallel multiplier and accumulator that performs multiplication and accumulation; A holding register that holds the parallel multiply-accumulate results. Multiple coordinate transformation units with It also has a coordinate conversion unit. Generates control data that controls the operation of the cut control means and output from the control means The control data that is It is supplied to each coordinate conversion unit by have timing control means to A coordinate conversion device characterized by: