JPS6379443A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To prevent deterioration in an eye pattern by detecting a detection signal sent prior to a data so as to increase the time constant of a threshold level setting circuit thereby allowing the titled equipment to cope with the fluctuation of a DC bias level at a high speed. CONSTITUTION:When no radio wave exists, an analog switch 5-9 of a threshold level setting circuit 5 is turned on and a time constant decided by a capacitor 5-1 and a resistor 5-6 is small. In receiving a radio wave and a signal whose DC bias level is fluctuated is given to a threshold level setting circuit 5, then a timing clock generating circuit 8 is started by an output of a bit synchronizing detection circuit 7 and an analog switch 5-9 is turned off. Then the time constant of the threshold level setting circuit 5 is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data transmission device that shapes the waveform of a Haasband signal whose waveform is distorted due to the influence of a transmission path.

BACKGROUND OF THE INVENTION In recent years, wireless data communication has become popular. In such wireless data communication, a data transmission device is required on the receiving side that has a waveform shaping circuit that converts a demodulated signal into a binary signal based on a certain threshold level.

An example of the above-mentioned conventional data transmission device will be described below with reference to the drawings.

FIG. 3 shows a block diagram of a conventional data transmission device. In Fig. 3, 1 is an antenna, 2 is a receiver,
3 is a demodulation circuit, 4 is a low-pass filter, 5 is a threshold level setting circuit, 6 is a voltage comparison circuit, 7 is a bit detection circuit, 8 is a timing clock generation circuit, 9 is a data extraction circuit, 10 is data end detection circuit,
11 is a micro convenience store. The threshold level setting circuit 5 includes a time constant circuit composed of a capacitor 5-1 and a resistor 5-2, and a voltage source 5-3 that provides a constant DC voltage.

The operation of the data transmission device configured as described above will be explained below. Table 1 is an excerpt from the standards office for micro-power low-speed data transmission systems that came into effect in June 1986.

Table 1 (Note) (1) The bit synchronization signal is rib rOJ
Let the signals be arranged alternately.

(2) The frame synchronization signal shall be a 31-bit M-sequence code.

The radio wave is received by the receiver 2, and the receiver 2 outputs an FSX-modulated 450 KHz φ open wave signal. The intermediate frequency signal is subjected to FSX demodulation in a demodulation circuit 3. As the demodulation circuit 3, for example, a Claude Ratcher detection method, which is a type of frequency detection, is used. FSX with demodulation circuit 3
The modulated signal is demodulated and output as a 4800 bps NRZ baseband signal. The NRZ baseband signal has noise components outside the band removed by a low-pass filter 4, and is input to a threshold level setting circuit 5.

In the threshold level setting circuit 5, the capacitor 5
-1, the configuration is such that the DC component is removed.

Next, the NRZ baseband signal is waveform-shaped into a binary signal by the voltage comparator circuit 6 and inputted to the focus synchronization detection circuit 7. The bit synchronization detection circuit 7 detects bit synchronization by, for example, detecting a bit synchronization signal by counting the number of zero crossing points within a certain period of time. H
Set it to 4gh. Then, the timing clock generation circuit 8 operates and outputs a timing clock synchronized with the bit synchronization signal. The data extraction circuit 9 latches the signal from the voltage comparison circuit 6 using the timing clock from the timing clock generation circuit 8 and outputs it.

The data end detection circuit 10 detects the end of the data, and the bit synchronization detection circuit 7 is reset. The end of data can be detected by, for example, sending data specifying the number of bits to be transmitted after frame synchronization and counting the number of focus points, or by determining an end code and detecting the end of the data when the end code arrives. A method of detecting the end is used. Note that the circuits 7, 8, 9, and 10 can be easily configured using the microcomputer 11.

Problems to be Solved by the Invention However, the above configuration has the following problems. That is, the NRZ baseband signal contains energy up to the DC component.

Therefore, unless the time constant determined by the capacitor 5-1 and the resistor 5-2 is made sufficiently larger than the length determined by the transmission speed of 4800 bps, the energy of the low frequency component will be lost, causing deterioration of the eye pattern. As a result, the bit error rate deteriorates, which is undesirable. However, if the time constant determined by the capacitor 5-1 and the resistor 5-2 is increased, the signal applied to the positive input of the voltage comparator circuit 6 becomes
It becomes like l. FIG. 6 will be explained. Figure 6 (a
l indicates a change in the DC bias level of the demodulation circuit 3. FIG. 6 fb) shows the waveform after the NRZ baseband signal is superimposed on the DC bias level and passes through the capacitor 5-1. In Figure 6, when a radio wave is received from the non-receiving state where no radio wave is being received, reception 8!1
Due to an error in the intermediate frequency signal from the regular intermediate frequency caused by an error in the local oscillation frequency of 2 or an adjustment error in the demodulation center frequency of the demodulation circuit 3, the DC bias level of the demodulation circuit 3 is changed as shown in Fig. 6 1a). A phenomenon occurs in which the value fluctuates.

Therefore, if the time constant determined by the capacitor 5-1 and the resistor 5-2 is large, the differential waveform will have an NR value as shown in Figure 6 (bl).
The Z baseband signal is superimposed. Therefore, it takes as long as the bit synchronization signal period until the zero crossing point of the NRZ baseband signal stabilizes at the threshold level determined by the voltage source 5-3. Therefore, there was a problem in that the bit synchronization signal was not outputted to the output of the voltage comparison circuit 6, and therefore subsequent data could not be received.

In view of the above-mentioned problems, the present invention provides a data transmission device having a threshold level setting circuit that can quickly respond to fluctuations in the DC bias level of a demodulation circuit during data reception and that does not cause deterioration of the eye pattern. It is.

Means for Solving the Problems In order to solve the above problems, the data transmission device of the present invention includes a signal detection circuit that detects a detection signal sent prior to data, and a binary system that converts data from a transmission path into a binary signal. a voltage comparator circuit that shapes a waveform into a waveform, and a time constant circuit that is connected between the voltage comparator circuit and the transmission line and controls the DC component in the signal from the transmission line by the output of the signal detection circuit. The present invention is equipped with a threshold level setting circuit that sets the level of the zero crossing point of the alternating current component in the signal as a threshold level.

Effect of the present invention With the above-described configuration, the time constant of the threshold level setting circuit is kept small until the detection signal sent prior to the data (also used as a bit synchronization signal in this embodiment) is detected. By increasing the time constant when an optical signal is detected, it is possible to quickly respond to fluctuations in the DC bias level without causing deterioration of the eye pattern.

Embodiment Hereinafter, a data transmission device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a data transmission device in a first embodiment of the present invention. In Figure 1, the third
Blocks showing the same functions as the conventional example shown in the figure are given the same numbers as in FIG. The difference between the conventional example shown in FIG. 3 and the embodiment shown in FIG. 1 is the configuration of the threshold level setting circuit 5. Therefore, the configuration and operation of threshold level setting circuit 5 will be mainly explained.

5-1 is a capacitor, 5-2 and 5-6 are resistors, 5-
7. 5-8 is a diode, and 5-9 is an analog switch. 5-3 is a voltage source. The threshold level setting circuit 5 will be explained with reference to FIG. Figure 4 corresponds to Figure 6, and Figure 4 (al
indicates the change in the DC bias level of the demodulation circuit 3, and the fourth
Figure (bl) shows the waveform after the NRZ baseband signal is superimposed on the DC bias level and passes through the capacitor 5-1. First, when there is no radio wave, the analog switch 5-9 is in the ON state. 5-6 resistance value R5-6
, if the resistance value of resistor 5-2 is R5-2, then R5-6<<
It is set as R5-2. Therefore, when the analog switch 5-9 is ON, the capacitor 5-1 and the resistor 5-
The time constant determined by 6 is small.

When a radio wave is received in this state and a signal with a fluctuating DC bias level as in No. 41E11a+ is input to the threshold level setting circuit 5, the time constant is small as described above, so the high speed The diode 5-7 and 5-8 are used to absorb fluctuations in the DC bias level that are higher than the diode voltage.Therefore, even if only a part of the bit synchronization signal is destroyed, the voltage comparator circuit 6 A signal below bit synchronization whose waveform has been shaped into a binary signal is output.The bit synchronization signal is detected by the bit synchronization detection circuit 7, starts the timing clock generation circuit 8, and turns off the analog switch 5-9.
Make it F. Then, the time constant of the threshold level setting circuit is determined by the capacitor 5-1 and the resistor 5-2. Time t in FIG. 4('b) indicates the time when the time constant changes. The time constant determined by the capacitor 5-1 and resistor 5-2 is
The value is set to a value large enough to prevent eye pattern deterioration. For example, for an NRZ baseband signal of 4.800 bps, the value of capacitor 5-1 is 10μF.
, the value of the resistor 5-2 is set to 100Ω, and the value of the resistor 5-6 is set to 100Ω.

As described above, according to this embodiment, the bit synchronization detection circuit 7
By providing the threshold level setting circuit 5 whose time constant is controlled by a signal from equipment can be provided.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a data transmission device showing a second embodiment of the present invention. In this figure, blocks showing the same functions as in FIG. 1 are given the same numbers. The difference from FIG. 1 is the configuration of the threshold level setting circuit 5. Therefore, the configuration and operation of the threshold level setting circuit 5 will be mainly explained below.

5-9 is an analog switch, 5-10 is a capacitor, 5
-11 and 5-12 are resistors, 5-13 and 5-14
is a diode. The threshold level setting circuit 5 will be explained with reference to FIG. Figure 5 corresponds to Figures 4 and 6, and Figure 5 (al
indicates the change in the DC bias level of the demodulation circuit 3, and the fifth
Figure (bl) shows a waveform in which the NRZ Hazband signal is superimposed on the DC bias level. First, when there is no radio wave, the analog switch 5-9 is in the ON state. Resistor 5
If the resistance value of -11 is R5-11' and the resistance value of resistor 5-12 is R5-1, then R5-1! <<It is set as R5-11. Therefore, when the analog switch 5-9 is in the ON state, the time constant determined by the capacitor 5-10 and the resistor 5-12 is small. Consider the case where a radio wave is received in this state and a signal with a fluctuating DC bias level is input to the threshold shield level setting circuit 5 as shown in FIG. A waveform in which the NRZ signal is superimposed on the NRZ signal in FIG. A signal at the threshold level shown by the dotted line in Figure 5 tbl is input.Now, as described above (resistor 5
Since the time constant determined by -12 and capacitor 5-10 is small, the threshold level signal quickly becomes stable as shown by the dotted line in FIG. 5 tbl.

Note that the diodes 5-13, 5-14 are provided to immediately follow fluctuations in DC bias higher than the diode voltage. By the above operation, only a part of the bit synchronization signal is destroyed, and the voltage comparator circuit 6 outputs a signal whose waveform is shaped into a binary signal and which is less than the bit synchronization signal. The focus synchronization signal is detected by the focus synchronization detection circuit 7, which activates the timing clock generation circuit 8 and turns off the analog switch 5-9. Then, the time constant of the threshold level setting circuit is determined by the capacitor 5-10 and the resistor 5-11. Time t in FIG. 5 tb+ indicates the time when the time constant changes. The time constant determined by the capacitor 5-10 and the resistor 5-11 is set to a large value so that the signal applied to the negative input terminal of the voltage comparator circuit 6 will not be fluctuated by the NRZ Haasband signal. Therefore, the voltage comparison circuit 6
The eye pattern is not degraded during binarization.

As described above, according to the second embodiment, by providing the threshold level setting circuit 5 whose time constant is controlled by the signal from the bit synchronization detection circuit 7, it is possible to follow fluctuations in the DC bias level at high speed. Therefore, it is possible to provide a data transmission device that reliably performs bit synchronization detection and at the same time does not cause eye pattern deterioration.

Effects of the Invention As described above, the present invention provides a signal detection circuit that detects a detection signal sent before data, a voltage comparison circuit that shapes data from a transmission line into a binary waveform, and the voltage comparison circuit. and the transmission line, the DC component in the signal from the transmission line is removed using a time constant circuit controlled by the output of the signal detection circuit, and the zero crossing point of the AC component in the signal is removed. By providing a threshold level setting circuit that uses the level as a threshold level, it is possible to quickly respond to fluctuations in the DC bias level and to perform reliable bit synchronization detection, while at the same time providing data without eye pattern deterioration. A transmission device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data transmission device in a first embodiment of the present invention, FIG. 2 is a block diagram of a data transmission device in a second embodiment of the invention, and FIG. 3 is a block diagram of a conventional data transmission device. Pro 7 diagram, Fig. 4 (al, (bl is the operation explanatory diagram of Fig. 1, Fig. 5 (al), (bl is the operation explanatory diagram of Fig. 2, Fig. 6 (al, (bl is the operation explanatory diagram of Fig. 3) It is an explanatory diagram of the operation of the figure. 1...Antenna, 2...Receiver, 3.
... Demodulation circuit, 4 ... Low pass filter, 5 ... Threshold level setting circuit, 6
... Voltage comparison circuit, 7 ... Bit synchronization detection circuit, 8 ... Timing clock generation circuit, 9 ... Data extraction circuit, Engineering 0 ... ... Data end detection circuit, 11 ... Microcomputer, 5-1 ... Capacitor, 5-2 ...
...Resistance, 5-3...Voltage source, 5-6...
...Resistance, 5-7. 5-8...Diode,
5-9...Analog switch, 5-10...
... Capacitor, 5-11.5-12 ... Resistor, 5-13.5-14 ... Diode. Agent's name Patent attorney Toshio Nakao One idiot Figure 4 Kofo Gingin Bit Shoulder Period Fram Shoulder η Data Book

Claims (1)

[Claims] a signal detection circuit that detects a detection signal sent before data; a voltage comparison circuit that shapes data from a transmission line into a binary waveform; connected between the voltage comparison circuit and the transmission line; A threshold that removes the DC component in the signal from the transmission path using a time constant circuit controlled by the output of the signal detection circuit and sets the level of the zero crossing point of the AC component in the signal as a threshold level. A data transmission device comprising a level setting circuit.