JPS6379365A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6379365A JPS6379365A JP61223577A JP22357786A JPS6379365A JP S6379365 A JPS6379365 A JP S6379365A JP 61223577 A JP61223577 A JP 61223577A JP 22357786 A JP22357786 A JP 22357786A JP S6379365 A JPS6379365 A JP S6379365A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor chip
- wiring
- semiconductor device
- semiconductor chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 229920001721 polyimide Polymers 0.000 claims abstract 2
- 239000009719 polyimide resin Substances 0.000 claims abstract 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims 1
- 239000011229 interlayer Substances 0.000 claims 1
- 229910000881 Cu alloy Inorganic materials 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910000833 kovar Inorganic materials 0.000 abstract description 2
- 229910045601 alloy Inorganic materials 0.000 abstract 1
- 239000000956 alloy Substances 0.000 abstract 1
- 238000001816 cooling Methods 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000002826 coolant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に係り、特に、半導体装置の冷却
及び高速化技術に適用して有効な技術に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to cooling and speeding up a semiconductor device.
半導体装置の一つである高密度なフリップ・チップ方式
のフェイスダウン・ボンディングを採用したＬＳＩ等の
マルチ・チップ・モジュールでは、半導体チップの冷却
は、フェイスダウン・ボンディング用突起電極（以下、
単に、バンプという）を通して放熱させるのみで行われ
ている。この放熱手段だけでは、前記バンプの熱抵抗が
大きいため、チップの放熱性が悪く、これが半導体装置
の信頼性の低下及び短寿命の原因となっているため、半
導体チップの発生する熱が半導体回路の電気特性に影ｇ
を与えないようにする半導体チップの別の冷却手段を必
要とする。In multi-chip modules such as LSIs that employ high-density flip-chip type face-down bonding, which is a type of semiconductor device, semiconductor chips are cooled using protruding electrodes for face-down bonding (hereinafter referred to as
This is done simply by dissipating heat through the bumps. If only this heat dissipation means is used, the heat dissipation of the chip is poor due to the large thermal resistance of the bumps, which causes a decrease in the reliability and short life of the semiconductor device. influence on the electrical properties of
Another means of cooling the semiconductor chip is required to prevent the damage.
そこで、接触不良を防止する球状部を有する金属等の熱
伝導性のよいピストンを半導体チップの主面と反対側の
表面に接触させ、該半導体チップの発生する熱を外部に
放出する冷却技術が提案されている。（日経マグロウヒ
ル社発行、「日経エレクトロニクスＪ、１９８２年７月
１９日号、１］２３３〜Ｐ２５２の記載を参照）
〔発明が解決しようとする問題点〕
しかしながら、かかる技術を検討した結果、次のような
問題点を見い出した。Therefore, a cooling technology is developed in which a piston with good thermal conductivity, such as a metal piston with a spherical part to prevent contact failure, is brought into contact with the surface opposite to the main surface of the semiconductor chip, and the heat generated by the semiconductor chip is released to the outside. Proposed. (Refer to Nikkei Electronics J, July 19, 1982 issue, 1] 233-252, published by Nikkei McGraw-Hill) [Problems to be solved by the invention] However, as a result of examining such technology, the following I found a problem like this.
（１）前記冷却技術では、ピストン等を介在させて冷却
媒体に放出する手段のため実装密度が上がらず、かつ冷
却技術の信頼性が乏しい。また、前記冷却技術を簡素化
した場合、半導体チップのフリップ・チップ・ボンディ
ング用突起ｆｆ１ｔｌ側（主体側）からの放熱が十分で
ないため、特に、チップサイズを大きくした場合、前記
突起電極が破損してしまう。(1) In the above-mentioned cooling technology, the packaging density cannot be increased because a piston or the like is used to discharge the heat to the cooling medium, and the reliability of the cooling technology is poor. In addition, when the cooling technology is simplified, heat dissipation from the flip chip bonding protrusion ff1tl side (main body side) of the semiconductor chip is not sufficient, so especially when the chip size is increased, the protrusion electrode may be damaged. It ends up.
（２）前記基板の配線間の絶縁層を薄くして前記突起電
極側からの放熱性を良くすることはできるが、絶縁層を
薄くすると、浮遊容量が太き（なって高速化に対応する
ことができない。(2) It is possible to improve heat dissipation from the protruding electrode side by making the insulating layer between the wirings on the board thinner, but if the insulating layer is made thinner, the stray capacitance becomes thicker (which makes it difficult to cope with higher speeds). I can't.
本発明の目的は、半導体チップの放熱性を向上するこが
できる技術を提供することにある。An object of the present invention is to provide a technique that can improve the heat dissipation of a semiconductor chip.
本発明の他の目的は、半導体装置の高速化を図るこがで
きる技術を提供することにある。Another object of the present invention is to provide a technique that can increase the speed of a semiconductor device.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を説明すれば、下記のとおりである。Outline of typical inventions disclosed in this application is as follows.
すなわち、基板の表面と半導体チップの主面とが略同一
平面となるように、半導体チップを基板に埋込み、前記
基板の表面及び半導体チップの主面上に前記半導体チッ
プと電気的に接続する配線を施したものである。That is, the semiconductor chip is embedded in the substrate so that the surface of the substrate and the main surface of the semiconductor chip are substantially on the same plane, and wiring electrically connected to the semiconductor chip is provided on the surface of the substrate and the main surface of the semiconductor chip. It has been subjected to
前記した手段によれば、半導体チップの主面を基板の表
面に略同一平面となるように埋込み、前記基板の表面及
び半導体チップの主面上に前記半導体チップと電気的に
接続する配線を施したことにより、半導体チップの主面
以外の表面が基板と接触しているため、前記半導体チッ
プで発生した熱を前記基板に効率よく放熱するので、前
記突起電極の破損を低減することができる。According to the above-described means, the main surface of the semiconductor chip is buried in the surface of the substrate so as to be substantially flush with each other, and wiring electrically connected to the semiconductor chip is provided on the surface of the substrate and the main surface of the semiconductor chip. As a result, since the surface of the semiconductor chip other than the main surface is in contact with the substrate, the heat generated in the semiconductor chip is efficiently radiated to the substrate, so that damage to the protruding electrodes can be reduced.
また、前記半導体チップの放熱を前記基板に効率よく行
うことができることにより、配線を基板及び半導体チッ
プの主面」二に設けることができるため、配線間の絶縁
膜を厚くすることができるので、浮遊容量が小さくなり
高速化を図ることができる。Furthermore, since the heat of the semiconductor chip can be efficiently dissipated to the substrate, wiring can be provided on the main surfaces of the substrate and the semiconductor chip, and the insulating film between the wiring can be thickened. Stray capacitance is reduced and high speed can be achieved.
以下、本発明を一実施例とともに説明する。The present invention will be described below along with an example.
なお、全回において、同一の機能を有するものは同一の
符号を付け、その緑り返しの説明は省略する６
〔実施例〕
第１図は、本発明の半導体装置の概略構成を示す平面図
、
第２図は、第１図に示す■−ＩＩ切断線で切った断面図
である。In all episodes, parts having the same functions are given the same reference numerals, and explanations of the red and green parts are omitted.6 [Example] Fig. 1 is a plan view showing a schematic configuration of a semiconductor device of the present invention. , FIG. 2 is a cross-sectional view taken along the line II--II shown in FIG. 1.
本実施例の半導体装置は、第１図及び第２図に示すよう
に、導電性のアルミニウム、銅合金、コバール、４２７
０イ等から成る熱伝導性のよい基板１に埋込み穴ＩＡを
設け、この埋込み穴ＩＡに半導体チップ２をその主面２
Ａと前記基板１とが酩同一平面となるように熱伝導性の
良いペース１−３を介在させて埋込んである。As shown in FIGS. 1 and 2, the semiconductor device of this example is made of conductive aluminum, copper alloy, Kovar, 427
A buried hole IA is provided in a substrate 1 with good thermal conductivity made of a material such as 0, and a semiconductor chip 2 is inserted into the buried hole IA on its main surface
A paste 1-3 having good thermal conductivity is interposed and embedded so that A and the substrate 1 are on the same plane.
前記基板ｌに設けられた埋込み六１Ａは、前記半導体チ
ップ２が一定のピッチで精度よく並ぶように形成されて
いる。そして、前記基板１の表面及び半導体チップ２の
主面上にボリミイト樹脂等から成る第１絶縁膜４を設け
、この第１絶縁ｌ１２４上に第１配線５を設け、この第
１配線５と前記半導体チップ２の主面上に設けられた電
極２Ｂと電気的に接合している。The recesses 1A provided in the substrate 1 are formed so that the semiconductor chips 2 are lined up accurately at a constant pitch. Then, a first insulating film 4 made of volimiite resin or the like is provided on the surface of the substrate 1 and the main surface of the semiconductor chip 2, and a first wiring 5 is provided on this first insulating film 124. It is electrically connected to an electrode 2B provided on the main surface of the semiconductor chip 2.
また、前記絶！１１′ｌＡ４に加工性の良いボリミイド
樹脂等を用いることにより、前記基板１と半導体チップ
２の主面との高さが少しずれて段差があっても第１絶縁
膜４を精度よく容易に形成することができる。Also, unprecedented! By using borimide resin or the like with good workability for 11'lA4, the first insulating film 4 can be easily formed with high precision even if there is a slight difference in height between the substrate 1 and the main surface of the semiconductor chip 2 and a step difference. can do.
前記第１配ａ５の上には、第２絶縁膜６を介在させて第
２配線７が多層配線される。A second wiring 7 is formed in multiple layers on the first wiring a5 with a second insulating film 6 interposed therebetween.
また、前記熱伝導性の良いペース１−３のかわりに導電
性のペーストを用い、かつ、前記半導体チップ２のグラ
ンド線を前記埋込み穴１Δの底面に接触するようにすれ
ば、マイクロ・ストリップ化できるので、半導体チップ
２のインピーダンス整合を容易に行うことができる。Furthermore, if a conductive paste is used instead of the paste 1-3 having good thermal conductivity, and the ground wire of the semiconductor chip 2 is brought into contact with the bottom surface of the embedded hole 1Δ, a micro strip can be formed. Therefore, impedance matching of the semiconductor chip 2 can be easily performed.
以上の説明かられかるように、この実施例によれば、次
の効果を奏することができる。As can be seen from the above description, according to this embodiment, the following effects can be achieved.
（１）基板１の表面と半導体チップ２の主面２Ａとが略
同一平面となるように、半導体チップ２を基板ｌに埋込
み、前記基板１の表面及び半導体チップ２の主面上に前
記半導体チップ２と電気的に接続する第１配線及び第２
配線５．７を施したことにより、半導体チップ２の主面
２Δ以外の表面が基板１と接触とているため、前記半導
体チップ２で発生した熱を前記基板２に効率よく放熱す
るので、パッケージの熱抵抗を大幅に低減でき、大電力
化、高集積化、埋め込みチップの大面積化が可能となる
。(1) The semiconductor chip 2 is embedded in the substrate l so that the surface of the substrate 1 and the main surface 2A of the semiconductor chip 2 are approximately on the same plane, and the semiconductor A first wiring and a second wiring electrically connected to the chip 2.
By providing the wiring 5.7, the surface of the semiconductor chip 2 other than the main surface 2Δ is in contact with the substrate 1, so that the heat generated in the semiconductor chip 2 is efficiently radiated to the substrate 2. Thermal resistance of the device can be significantly reduced, making it possible to increase power consumption, increase integration, and increase the area of embedded chips.
（２）前記半導体チップ２の放熱を前記基板１に効率よ
く行うことができることにより、第１配線及び第２配線
５．７を基板１及び半導体チップ２の主面２Ａ上に設け
ることができるため、第１配線及び第２配線５，７間の
第１絶縁暎及び第２絶縁膜４，６を厚くすることができ
るので、浮遊容量が小さくなり半導体装置の高速化を図
ることができる。(2) Since the heat of the semiconductor chip 2 can be efficiently dissipated to the substrate 1, the first wiring and the second wiring 5.7 can be provided on the main surface 2A of the substrate 1 and the semiconductor chip 2. Since the first insulating film and the second insulating films 4 and 6 between the first wiring and the second wiring 5 and 7 can be made thicker, the stray capacitance is reduced and the speed of the semiconductor device can be increased.
以上、本発明を実施例にもとすき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変形可能であること
はいうまでもない。The present invention has been specifically explained above using examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
基板の表面と半導体チップの主面とが略同一平面となる
ように、半導体チップを基板に埋込み、前記基板の表面
及び半導体チップの主面上に前記半導体チップと電気的
に接続する配線を施したことにより、半導体チップの主
面以外の表面が基板と接触とているため、前記半導体チ
ップで発生した熱を前記基板に効率よく放熱するので、
パッケージの熱抵抗を小さくすることができる。A semiconductor chip is embedded in a substrate so that the surface of the substrate and the main surface of the semiconductor chip are substantially on the same plane, and wiring electrically connected to the semiconductor chip is provided on the surface of the substrate and the main surface of the semiconductor chip. As a result, the surface other than the main surface of the semiconductor chip is in contact with the substrate, so that the heat generated in the semiconductor chip is efficiently radiated to the substrate.
The thermal resistance of the package can be reduced.
また、前記半導体チップの放熱を前記基板に効率よく行
うことができることにより、配線を基板及び半導体チッ
プの主面上に設けることができるため、配線間の絶縁膜
を厚くすることができるので、浮遊容量が小さくなり半
導体装置の高速化を図ることができる。In addition, since the heat of the semiconductor chip can be efficiently dissipated to the substrate, wiring can be provided on the main surface of the substrate and the semiconductor chip, and the insulation film between the wiring can be thickened. The capacitance is reduced and the speed of the semiconductor device can be increased.
第１図は、本発明の半導体装置の概略構成を示す平面図
。
第２図は、第１図に示すＩＴ −１１切断線で切った断
面図である。FIG. 1 is a plan view showing a schematic configuration of a semiconductor device of the present invention. FIG. 2 is a sectional view taken along the IT-11 cutting line shown in FIG.
Claims (1)
なるように、半導体チップを基板に埋込み、前記基板の
表面及び半導体チップの主面上に前記半導体チップと電
気的に接続する配線を施したことを特徴とする半導体装
置。 ２、前記半導体チップは、熱伝導性の良いペースト等を
介して埋込まれていることを特徴とする特許請求の範囲
第１項に記載の半導体装置。 ３、前記配線は、多層配線であることを特徴とする特許
請求の範囲第１項又は第２項に記載の半導体装置。 ４、前記配線は、該層間膜にポリイミド樹脂等の加工性
の良い絶縁物を用いたことを特徴とする特許請求の範囲
第１項乃至第３項の各項に記載の半導体装置。 ５、前記基板は、金属であることを特徴とする特許請求
の範囲第１項乃至第４項の各項に記載の半導体装置。[Claims] 1. A semiconductor chip is embedded in a substrate so that the surface of the substrate and the main surface of the semiconductor chip are substantially on the same plane. A semiconductor device characterized by having wiring for electrical connection. 2. The semiconductor device according to claim 1, wherein the semiconductor chip is embedded through a paste or the like having good thermal conductivity. 3. The semiconductor device according to claim 1 or 2, wherein the wiring is a multilayer wiring. 4. The semiconductor device according to any one of claims 1 to 3, wherein the wiring uses an insulating material with good processability, such as polyimide resin, for the interlayer film. 5. The semiconductor device according to any one of claims 1 to 4, wherein the substrate is made of metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61223577A JPS6379365A (en) | 1986-09-24 | 1986-09-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61223577A JPS6379365A (en) | 1986-09-24 | 1986-09-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6379365A true JPS6379365A (en) | 1988-04-09 |
Family
ID=16800343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61223577A Pending JPS6379365A (en) | 1986-09-24 | 1986-09-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6379365A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5359496A (en) * | 1989-12-21 | 1994-10-25 | General Electric Company | Hermetic high density interconnected electronic system |
| US5452182A (en) * | 1990-04-05 | 1995-09-19 | Martin Marietta Corporation | Flexible high density interconnect structure and flexibly interconnected system |
| WO2009127300A1 (en) * | 2008-04-16 | 2009-10-22 | Rohde & Schwarz Gmbh & Co. Kg | Microwave assembly |
-
1986
- 1986-09-24 JP JP61223577A patent/JPS6379365A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5359496A (en) * | 1989-12-21 | 1994-10-25 | General Electric Company | Hermetic high density interconnected electronic system |
| US5452182A (en) * | 1990-04-05 | 1995-09-19 | Martin Marietta Corporation | Flexible high density interconnect structure and flexibly interconnected system |
| EP0450950B1 (en) * | 1990-04-05 | 2001-11-21 | Lockheed Martin Corporation | A flexible high density interconnect structure |
| WO2009127300A1 (en) * | 2008-04-16 | 2009-10-22 | Rohde & Schwarz Gmbh & Co. Kg | Microwave assembly |
| US8288864B2 (en) | 2008-04-16 | 2012-10-16 | Rohde & Schwarz Gmbh & Co. Kg | Microwave module |
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