JPS6376650A - Communication control processor - Google Patents

Abstract

PURPOSE:To completely supervise data on a bus by employing dual one-chip microcomputers for a communication control processing part and using the one dedicated to the communication control processing of a transmission line and the other dedicated to the communication processing to a inner processing. CONSTITUTION:An IFU control processing part 12 is realized with the one-chip microcomputer having dual CPUs 14 and 16. The data 31a on the bus is received 33a by a bis data exchange processing part 15, a terminal data exchange processing part 17 is activated through a shared memory area 18, and a transmission processing 34a to the terminal is executed. At the time, the bus data exchange processing part 15 is ready 22a for the bus, and therefore it can receive the data on the bus anytime regardless of transmission processing time to the terminal. Even if the transmission processing 34a to the terminal takes longer than a recess time 32a on the bus, the bus data exchange processing part 15 can receive 32b the data 31b on the bus.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a communication system in which a plurality of terminals are connected to pair wires, coaxial cables, etc. and mutually transmit information. This invention relates to a communication control device in a large-scale system.

Conventional technology A conventional communication control device will be explained with reference to the drawings.

FIG. 5 shows an example of the configuration of a home bus system to which the communication control processing device of the present invention is applied, FIG. 6 shows an example of the configuration of data on a transmission path in the home bus system, and FIG. An example of the configuration of a control processing device is shown in FIG. 8, a state transition diagram of a conventional communication control processing device, and FIG.
An example of a related diagram of data transmission/reception processing to a terminal is shown.

Conventional communication control unit (hereinafter referred to as IFU) (Fig. 555)
As shown in FIG. 7, a to 65C) are composed of a bus I10 processing section 73, an IFU control processing section 72, and a terminal I10 processing section 71, and the IFU control processing section 72 is realized by a single central processing unit (CPTR). , a bus data transmission/reception control processing section 74, a terminal data transmission/reception control processing section 75, and a transmission/reception data buffer 76. I of this configuration
When the power is turned on, the FU enters a standby state 81&. Here, when a data transmission request is received from the terminal (56a to 56c in FIG. 5), the terminal data transmission/reception processing section 76 is activated in the control processing section 72 of the IFU 55a to 55C, and the state becomes the terminal data reception processing state 81d. Data from the bus is not accepted. When the data reception from the terminal is completed, the bus data transmission/reception processing unit 7 sends the existing data to the bus.
4 is activated and the state shifts to bus data transmission processing state 81C. Regarding reception of data from the bus, the control processing unit 7
2, the bus data transmission/reception processing section 74 is activated in response to an interrupt from the bus, and the state is the bus data reception processing state 81b.
During this time, data from the terminal will not be accepted. When the data reception from the bus is completed, the terminal data transmission/reception processing section 75 is activated to transmit the existing data to the terminal, and the state shifts to the terminal data transmission processing state 81e, during which no bus data is accepted.

A case will be described with reference to FIG. 9 about a case where data addressed to the terminal is continuously transmitted on the bus and the process of transmitting the received data from the bus to the terminal takes longer than the pause time on the bus. If the data 91a on the bus is received 93&, and the transmission process 94& to the terminal takes longer than the idle time 92N on the bus, the terminal data transmission/reception processing section 75 is activated in the IFU during that time, so no data on the bus is transmitted. No reception. Therefore, the next data 91t) on the bus cannot be received, and the IFU on the sending side performs retransmission processing to send data 91t).
Send.

61.-Problems to be Solved by the Invention The above prior art has the following problems. - Since communication with the terminal is impossible during data transmission/reception processing on the bus, the terminal side must perform troublesome processing such as retransmission in order to determine whether or not the device is malfunctioning. ■IF
When U is used for security management, etc., internal processing is not possible while data on the bus is being monitored, resulting in processing delays. ■Communication on the bus becomes impossible while data is being sent and received from the terminal, and if communication with the terminal takes a long time, data on the bus may be dropped, and if retransmission is performed, communication efficiency decreases. invite. ■The data that was dropped is
If the data does not require a response and is related to the operation of the system, such as broadcast communication, only one terminal will behave contrary to the system, which may affect the reliability of the system. Missing.

Means for Solving the Problems In view of the problems of the above-mentioned conventional examples, the present invention connects a plurality of terminals to pair wires, coaxial cables, etc., and connects them to each other.

A dual 1-chip microcontroller is used in the data control processing section of the communication control device in a communication system that transmits information, allowing communication control processing on the bus and communication control processing on the terminal side to be performed independently without major changes to the hardware configuration. In order to make the system executable and increase the reliability of the system, a dual 1-chip microcontroller is used in the data control processing section of the communication control device in the communication system that transmits information between each other. The configuration is such that communication control processing on the bus and communication control processing on the terminal side can be executed independently without significantly changing the configuration of the node.

Effects The above solution not only eliminates the loss of data on the bus and increases the reliability of the system, but also allows sufficient time for internal processing (communication with terminals), making it usable for a wide variety of applications. It is something that has the effect of being.

Embodiment A case in which the communication control processing device of the present invention is applied to the existing system shown in FIG. 6 will be described with reference to FIGS. 1 to 4. FIG. 1 shows an example of the configuration of a communication control processing device according to the present invention, FIG. 2 is a state transition diagram of the communication control processing device, and FIG. 3 shows data on the bus in the communication control processing device shown in FIG. An example of a diagram relating to reception processing and internal processing (data transmission/reception processing to a terminal), FIG. 4 shows a block diagram of a data buffer for receiving and passing data between a bus side processing section and an end side processing section. IFUlo shown in FIG. 1 (corresponding to 55 in FIG. 5) includes a bus I10 processing section 13, an IFU control processing section 12, a terminal I1
The IFU control processing section 12 includes a dual GPU 14.

It is realized by a one-chip microcomputer having 16, and is composed of a bus data transmission/reception control processing section 15, a terminal data transmission/reception control processing section 17, and a common memory 18. When the power is turned on, there are two standby states inside rFtra; 6a to 56C: a pair-to-bus standby state 22& and a terminal-to-terminal standby state 23a-. When a data transmission request is received from the terminals 56a to 56.0, the terminal data transmission/reception processing unit 17 of the IFUs 55a to 550 enters the terminal data reception processing state 230 and performs data reception processing from the terminal. During this time, the bus data transmission/reception processing unit 15 is in a standby state 222L and operates independently of the terminal data transmission/reception processing unit 17, so that it can receive data even if there is data from the bus. When data reception from the terminal is completed, the bus data transmission/reception processing unit 15 is activated via the common memory area 18 to transmit the existing data to the bus, and enters the bus data transmission state 220. At this time, the terminal data transmission/reception processing unit 17 is in a terminal standby state 232L, and can receive data from the terminal at any time. Regarding the reception of data from the bus, the bus data transmission/reception processing unit 15 enters the bus data reception processing state 22b in response to an interrupt from the bus, and during this time the terminal data transmission/reception processing unit 17 is in the waiting state for the terminal. Data reception is possible. When the data reception from the bus is completed, the terminal data transmission/reception processing unit 17 is activated via the common memory area 18 in order to transmit the existing data to the terminal, and enters the terminal data transmission state 23b. At this time, the state of the bus data transmission/reception processing section 15 is the bus standby state 22&, and data can be received from the bus at any time.

A case will be described using FIG. 3 in which data addressed to the terminal is continuously transmitted on the bus and the process of transmitting the received data from the bus to the terminal takes longer than the pause time on the bus. After the data 31a on the bus is received 33a by the bus data transmission/reception processing unit 15, the data 31a is received in the common memory area 18.
The terminal data transmission/reception processing section 17 is activated via the terminal data transmission/reception processing section 17, and transmission processing 341L to the terminal is performed. At this time, the bus data transmission/reception processing unit 15 is already in the bus standby state 22&, so it can receive data on the bus at any time regardless of the transmission processing time to the terminal.

Therefore, even if the transmission process 34a to the terminal takes longer than the idle time 321L on the bus, the bus data transmission/reception processing unit 15 transmits the data 31b on the bus to the reception 32b.
is possible. Further, the configuration of the common memory 18 in the case of the configuration of this IFU is the same configuration 1o as the configuration of data on the bus shown in FIG.

^-7, and instead of the check code (61g in Figure 6), for data sent from the terminal, the transmission result is shown as a 1-byte response code (41 in Figure 4), and its contents are the response code on the bus. (63 in FIG. 6), it is possible to eliminate the increase in the number of buffers when two CPUs are used.

Effects of the Invention As described above, the present invention provides a communication system in which a plurality of terminals are connected to a pair of wires or a coaxial cable, etc., and mutually transmits information, and is particularly useful in small and medium-sized systems such as home bus systems. In the communication control device, it becomes possible to completely monitor the data on the bus, which not only increases the reliability of the system but also makes it usable for a wide variety of applications.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a communication control processing device according to an embodiment of the present invention, FIG. 2 is a state transition diagram of the device, and FIG. FIG. 4 is a configuration diagram of a data buffer for receiving and passing between a bus-side processing unit and a terminal-side processing unit, and FIG. 5 is a diagram of a conventional home bus to which the communication control processing device of the present invention is applied. Figure 6 is a configuration diagram showing an example of the system. Figure 6 is a configuration diagram of an example of data on the transmission path in the same home bus system.
The figure shows a configuration diagram of a conventional communication control processing device, Fig. 8 shows a state transition diagram of the device, and Fig. 9 shows the relationship between data reception processing on the bus and internal processing (data transmission/reception processing to a terminal) in the same device. It is a diagram. 1o...IFU, 11...Terminal I10
Processing unit, 12... CPU common memory, 13...
... bus data processing section, 14 ... IFU control processing section, 15 ... bus data processing section, 16.
...CPU-a, 17...CPU-b,
1B...CPU common memory. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 5 Figure 6 Figure 7 Figure 8

Claims (2)

[Claims] (1) In a system in which a plurality of terminals are connected via a transmission path and perform mutual communication according to a communication control method on the transmission path, a data transmission/reception processing unit transmits data transmitted and received on the transmission path to the terminal according to the communication method with the terminal. A terminal data transmission/reception processing unit is provided for transmitting and receiving terminal data, and each of the processing units is configured to operate independently, and a dual 1-chip microcomputer is used for the communication control processing unit, and one microcomputer is used for communication control processing of the transmission path. A communication control processing device characterized in that the other microcomputer is dedicated to internal processing and communication processing with a terminal. (2) Mutual communication between the data transmission/reception processing unit and the terminal data transmission/reception processing unit is performed by a common memory composed of a mutual status presentation flag area, a transmission/reception buffer management table area, and a transmission/reception buffer area, and the transmission/reception buffer The area has the same configuration as the data format on the transmission path, and the transmission result for data requested to be sent to the bus from the terminal data transmission/reception processing unit to the data transmission/reception processing unit is used as an area for data error confirmation such as sum checking of transmitted and received data. 2. The communication control processing device according to claim 1, wherein the communication control processing device is configured to receive and receive the communication control processing device.