JPS6376649A - Terminal adding device - Google Patents

Abstract

PURPOSE:To use a quick data terminal through a switching network whose transmission speed is low by segmenting quick data into blocks made of the fixed number of bits, distributing said blocks to plural switching network lines at different transmission speeds, cocurrently transmitting the data, serially synthesizing and reproducing it. CONSTITUTION:The quick data received from the quick data terminal 2 is segmented into blocks made of the fixed number of bits, and taken out them by a decomposing part of a terminal adding device 1. Frame bits are added to the blocks to form a frame. The blocks are sequentially distributed to plural lines 4-1, 4-2...4-N in the switching network 3 at a low transmission speed for the unit of the frame, and they are transmitted to the switching network 3. A phase detection part 12 detects the phase of each multiframe, and transmits the result to a synthesizing part 13. It adjusts the phase of each multiframe according to information, takes out the frames in the distribution order, excludes a frame bit, synthesizes the extracted blocks in serial, reproduces the quick data and transmits it to a data terminals 2'.

Description

[Detailed Description of the Invention] [Summary] High-speed data is divided into blocks each having a fixed number of bits, distributed to multiple switching network lines having a transmission speed lower than the transmission speed of the high-speed data, and transmitted in parallel. The resulting blocks are serially combined in the distribution order to reproduce high-speed data at the original transmission rate, so that a high-speed data terminal can be used in a switching network having a data transmission rate lower than the data transmission rate of the terminal. It is something to do.

[Industrial application field]

The present invention relates to a terminal attachment device that is attached to a high-speed data terminal and enables the high-speed data terminal to be used in a switching network by using a plurality of lines of the switching network having lines having a data transmission rate lower than the data transmission rate of the terminal. .

In a digital switching network, voice is handled as a digital signal, so data can be handled in the same way, and multimedia communication is provided that combines multiple media such as telephone and non-telephone.

The digital switching network is suitable for digitizing audio, for example 64K, because it uses a high-speed audio system.
Exchange is performed using bps digital signals, and the terminals connected to the line have the same or lower transmission speed.

However, high-speed data terminals such as color facsimiles with speeds of 64 Kbps or more have appeared, and in order to communicate with such high-speed data terminals over a digital switching network whose data transmission speed is lower than that of the terminal, multiple lines are required. Additional devices used in parallel to allow the terminal to communicate must be considered.

[Conventional technology]

Conventional terminal attachment equipment converts the data transmission speed of a terminal whose data transmission speed is slower than the data transmission speed of the switched network line to match the data transmission speed of the switched network line. High-speed data terminals that exceeded the speed could not be connected.

[The problem that the invention attempts to solve]

With conventional terminal attachment devices, data terminals with a data transmission speed up to the data transmission speed of the switching network line can be connected, but high-speed data terminals with a higher data transmission speed cannot connect to the switching network. There is a point.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, 2,2'' is a high-speed data terminal, 3 is a switching network, 4-L4-2...-5-N, 5-1.5-2
5-N is a line of the switching network 3.

1.1'' indicates a terminal additional device. According to the present invention, the numeral 11 divides high-speed data received from the high-speed data terminals 2, 2' into blocks each consisting of a certain number of bits, extracts them, adds frame bits to form a frame, and sends the high-speed data received from the high-speed data terminals 2, 2' to multiple blocks of the switching network 3. 12 is a switching network 3, which sequentially distributes frames to the lines 4-L4-2 to 4-N, forms a multi-frame for each line, and sends it out.
A phase detection unit 13 extracts frame bits from each frame of each multiframe received from a plurality of lines 5-1, 5-2...-5-N, and detects the phase of each multiframe; Adjust the phase of the multi-frames, extract frames from each multi-frame in the distribution order described above, remove the frame bits, synthesize the extracted blocks in series, reproduce high-speed data, and send the high-speed data terminals 2, 2 on the receiving side.
This is the synthesis section that sends the data to .

[Effect]

The high-speed data received from the high-speed data terminal 2 is extracted by the decomposition unit 11 of the terminal addition device 1 and divided into blocks consisting of a fixed number of focus points, frame bits are added to the blocks to form frames, and the high-speed data A plurality of lines 4-1.4-2...--4-N of the switching network 3 with a transmission rate lower than the data transmission rate of the terminal 2.
The data is sequentially distributed frame by frame, formed as a multiframe consisting of a plurality of frames for each line, and sent to the switching network 3.

Each multiframe is exchanged on the switching network 3, and each multiframe delayed by the switching process is transferred over the line 5-
1, 5-2...5-N and received by the phase detection section 12 of the terminal addition device 1°.

The phase detection section 12 detects the phase of each multiframe and sends the information to the synthesis section 13. The synthesis unit 13 adjusts the phase of each multi-frame according to the information, extracts frames from each multi-frame in the above distribution order, removes frame bits, synthesizes the extracted blocks in series, reproduces high-speed data, and reproduces high-speed data. Send to terminal 2°.

Thus, a high speed data terminal can be used in a switching network that uses a data transmission rate lower than the data transmission rate of the terminal.

〔Example〕

The present invention will be specifically explained below with reference to illustrated examples.

Fig. 2 is a block diagram of a data exchange system using a terminal addition device according to an embodiment of the present invention, Fig. 3 is an explanatory diagram of the configuration of high-speed data and multi-frames, and Fig. 4 is an explanatory diagram of multi-frame delay due to the exchange network. be. The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, serial-to-parallel conversion circuit 111. The parallel-to-serial conversion circuits 112 and 113 and the frame bit creation circuit 114 correspond to the decomposition unit 11 in FIG.
22 and the phase detection circuit 123 are the phase detection section 12 in FIG.
corresponds to Also, delay circuits 131, 132. The serial-to-parallel conversion circuits 133 and 134 and the parallel-to-serial conversion circuit 135 correspond to the combining section 13 in FIG.

For example, 112Kbp sent from the high-speed data terminal 2
As shown in FIG. 3(a), the high-speed data of s is divided into blocks of 7 bits each by the serial/parallel conversion circuit 111 and sent to the parallel/serial conversion circuit 112 with the first block D1 being 7 bits in parallel. , the next block D2 is sent to the parallel-to-serial conversion circuit 113, and the blocks after block D3 are similarly distributed alternately.

Frame bits (hereinafter referred to as F bits) are sent to the parallel-serial conversion circuits 112 and 113 from the frame bit creation circuit 114.
1 bit is sent in conjunction with the parallel transfer of said block;
A total of 8 bits form a frame.

The frames created one after another by the parallel-to-serial conversion circuits 112 and 113 are serially transmitted to lines 4-1 and 4-2, each having a data transmission rate of 64 Kbps, but a multi-frame set of 8 frames is used. is sent as a unit. That is, as shown in FIGS. 3(a) and 3(b), blocks Di, D3--D1 are output from the parallel-to-serial conversion circuit 112.
A multi-frame consisting of 8 frames including 5
A4-1, and thereafter multi-frames consisting of odd numbered blocks are sent out one after another.

From the parallel-to-serial conversion circuit 113, block D2. D4-DI
A multiframe consisting of 8 frames including 6 is sent to the line 4-2, and thereafter multiframes consisting of even numbered blocks are sent out one after another.

To identify a multi-frame, the F bit of the first frame of a multi-frame is set to “1#”, and the F bit of the following 7 frames is
The bit is set to "0".

The phases of the multiframe of line m4-1 and the multiframe of line 4-2 are the same as shown in FIG. As shown in FIG. 4(b), each multiframe of 2 is delayed in frame units due to the switching network, and the phases of the multiframes differ.

Lines 5-1 and 5-2 are connected to the serial-to-parallel converter circuit 121 and the serial-to-parallel converter circuit 122 of the terminal adder 1 on the receiving side, and both circuits extract the F bit from the received multiframe and detect the phase. to circuit 123.

The phase detection circuit 123 detects the F bit "
1" position to detect the phase difference between both multi-frames, and send delay control information to delay circuits 131 and 132.
Make adjustments so that the phases of both multi-frames are the same.

Both multi-frames that are in phase are each serial-parallel converter circuit 1
33 and serial/parallel converter circuit 134, and each frame is sent to 8
Although the data becomes bit parallel data, the F bit is removed here and the data is returned to a 7-bit block and sent to the parallel-to-serial conversion circuit 135.

The parallel-to-serial conversion circuit 135 assembles the blocks sent from the serial-to-parallel conversion circuit 133 and the serial-to-parallel conversion circuit 134 in the above-mentioned order of distribution (number order), converts them into serial data, sets the transmission speed to 112 Kbps, and converts the blocks to the original high-speed data. is played back and sent to the high-speed data terminal 2''.

〔Effect of the invention〕

As described in detail above, the present invention allows a high speed data terminal to be used in a switched network having a data transmission rate lower than the data transmission rate of the terminal.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of a data exchange system using a terminal addition device according to an embodiment of the present invention, Fig. 3 is an explanatory diagram of the configuration of high-speed data and multi-frames, and Fig. 4 is FIG. 3 is an explanatory diagram of multiframe delay caused by a switching network. In the figure, 1, 1'' is a terminal addition device, 2.2'' is a high-speed data terminal, 3 is a switching network, 4-1 to 4-N, 5-1 to 5-N are lines, 11 is a disassembly unit, 12 13 indicates a phase detection section, and 13 indicates a synthesis section.

Claims (1)

[Claims] High-speed data received from a high-speed data terminal (2, 2') is divided into blocks each consisting of a certain number of bits and extracted.
Frame bits are added to form a frame, and a plurality of lines (4-1, 4-2...4-
N), a disassembly unit (1
1), and a plurality of lines (5-1, 5-5) of the switching network (3).
a phase detection unit (12) that extracts the frame bits from each frame of the multiframes received from -2...5-N) and detects the phase of each multiframe; and adjusts the phase of each multiframe. Then, the frames are extracted from each multi-frame in the order of distribution, the frame bits are removed and the extracted blocks are serially combined to reproduce the high-speed data, and the high-speed data terminal (2, 2' 1.) A terminal adding device characterized in that it is provided with a combining unit (13) for sending data to a terminal.