JPS6376033A - Virtual memory system with variable memory size - Google Patents

Abstract

PURPOSE:To contrive to improve processing efficiency by changing the using range of a page table in accordance with the increase/decrease of a value in a memory size register. CONSTITUTION:A memory size increase/decrease circuit 18 increases/decreases a value in the memory size register 17 by a previously determined constant value on the basis of the compared result of a ratio of a garbage collection processing executing time within a fixed period with a threshold. The memory size of the fixed value to be assigned to a user is initially set up in the register 17 and the value is outputted to the circuit 18 and a page table control part 19. the control part 19 controls the using range of the page table 20 in accordance with the current value with the memory size stored in the register 17 to change the memory size. Consequently, the overhead of paging in the virtual storage and starting frequency of a gabage collector are balanced and the processing efficiency can be improved.

Description

[Detailed Description of the Invention] (Summary) In an information processing device equipped with a virtual memory and a garbage collector, the memory size of the virtual memory is made variable, and the overhead of paging in the virtual memory and the garbage collection processing time are balanced. Aim to improve performance.

[Industrial application field]

[Prior art and problems to be solved by the present invention] In general, in an information processing device using a virtual storage method, especially a LIST processor, etc., as processing progresses, As shown in FIG. 3, a large number of small free areas are generated in a distributed manner due to data deletion, etc., and it is normal that it becomes difficult to effectively utilize the allocated memory size. For this reason, a garbage collector is provided to perform garbage collection processing to collect free areas at appropriate timings, thereby increasing the efficiency of memory space.

In conventional information processing devices that have such virtual memory and a garbage collector, virtual memory is provided to the user until the addressable memory space is full, or virtual memory is provided to the user with a fixed memory size determined by the system. It provided virtual memory.

For this reason, both small and large programs are executed with the same memory size, so even though a small program can be executed only in real memory, it is executed in virtual memory. Paging overhead was causing long response times.

On the other hand, if only a small memory size is provided to a large program, the garbage collector will be started frequently, and the time required for garbage collection processing will be longer than the execution time of the processing processor, resulting in a decrease in execution performance. There was a problem with the decline.

[Means for solving problems]

The present invention reduces both the overhead of virtual memory paging and the time required for garbage collection processing by providing a memory size suitable for a program.
It provides high-speed execution performance.

The present invention proposes that when a small memory size is given to a program, the paging overhead is small, but the garbage collector is started frequently and execution performance deteriorates, whereas when a large memory size is given, the garbage collector is started. However, the overhead of paging increases and execution performance decreases, so the memory size is changed and controlled so that the garbage collector activation frequency is always a constant value to reduce both overheads. It is.

That is, in the present invention, the memory size is expanded when the frequency of the garbage collector is high, and conversely, the memory size is decreased when the t-negativity of the garbage collector is low.

FIG. 1 shows the basic configuration of the present invention.
is a CPU that executes user program processing and garbage collection processing.

2 is a first timer circuit, which measures the entire execution time of the CPU or the execution time other than garbage collection processing within the entire execution time. However, in FIG. 1, for convenience, the explanation will be given assuming that the total execution time is measured.

3 is a second timer circuit, which measures only the execution time of garbage collection processing.

Reference numeral 4 denotes a ratio calculating circuit, which calculates the ratio between the total execution time of the CPU measured by the first timer circuit 2 and the execution time of the garbage collection process measured by the second timer circuit 3.

Reference numeral 5 denotes a threshold value register, which holds a threshold value indicating an appropriate value of the ratio calculated by the ratio calculation circuit 4.

A comparison circuit 6 compares the ratio calculated by the ratio calculation circuit 4 with a threshold value to find a difference.

A memory size register 7 holds a value specifying the memory size of the virtual memory.

A memory size increase/decrease circuit 8 increases or decreases the value of the memory size register 7 based on the comparison result of the comparator circuit 6.

A page table control unit 9 controls the effective range of the page table 10 according to the value set in the memory size register 7.

[Effect]

In the configuration of the present invention shown in FIG.
A first timer circuit 2 is operated to measure the total execution time during a period in which some processing is being executed, and a second timer circuit 3 is operated particularly during a period in which garbage collection processing is being executed.

Next, the ratio (TG
/TC) is calculated by the ratio calculation circuit 4, and compared with the threshold value (represented by α) set in advance as an appropriate value in the threshold value register 5 by the comparison circuit 6, and (TG /TC) >α
, (TG/Tc)<α.

If (Tc/Tc)>α, that is, the proportion of the garbage collection processing execution time in the total execution time exceeds the appropriate value, the memory size increase/decrease circuit 8 is caused to increase the memory size. On the other hand, (T
If c/Tc)<α, reduce the memory size.

By increasing or decreasing the value of the memory size in this way, the page table control unit 9 changes the valid display of the page table 10, thereby controlling the increase or decrease of the memory size.

C Example] FIG. 2 shows the configuration of one embodiment of the present invention.

In the figure, 11 is the CPU, 12 is the CPU timer, 13
is a GC timer, 14 is a GC ratio calculation circuit, 15 is a threshold register, 16 is a comparison circuit, 17 is a memory size register, 1st is a memory size increase/decrease circuit, 19 is a page table control unit, 20 is a page table, 21 is an LRU circuit, 2
2 is an address register, 23 is a data register, 24 is an MSC (storage controller), 25 is an MS (storage device), 2
6 is a channel, and 27 is a disk device.

Note that the components indicated by 11 to 20 in FIG. 2 correspond to the components indicated by 1 to 10 in FIG. 1, respectively.

The CPU 1 sends and receives data to and from the MS 25 through an address register 22 and a data register 23. Also, when starting the garbage collector, in order to measure the execution time required for garbage collection processing,
The GC timer 13 is started, and the GC timer 13 is stopped when the garbage collection process ends. On the other hand, the CPU timer 12 is controlled to be stopped when the garbage collector is activated and started when the garbage collection process ends.

Thereby, the CPU timer 12 measures execution time other than garbage collection processing. Also, GC timer 1
3, only the execution time required for garbage collection processing is measured.

The MSC 24 performs memory access control and data transfer control between the MS 25 and the CPUI 1 or the channel 26.

The GC ratio calculation circuit 14 calculates the ratio of garbage collection processing execution time (GC ratio) within a certain period of time.

The threshold value register 15 holds a threshold value indicating an appropriate ratio of garbage collection processing execution time.

The comparison circuit 16 compares the GC ratio with the threshold value and outputs the result to the memory size increase/decrease circuit 1st.

The memory size increase/decrease circuit 18 performs an operation to increase/decrease the value of the memory size register 17 by a predetermined constant amount based on the comparison result. That is, when the GC ratio is high, the memory size increase/decrease circuit 18 increases or decreases the value of the memory size register 17 by a constant amount. , when the ratio is low, a certain amount is subtracted from the memory size value. As this fixed stage, it is sufficient to adopt several hundred KB or several MB.

The memory size register 17 is initially set with a fixed value allocated to the user, for example, a memory size of 4 MB or 16 MB, and this value is output to the memory size increase/decrease circuit 18 and the page table control section 19. The page table control unit 19 changes the memory size by controlling the usage range of the page table 20 according to the current value of the memory size in the memory size register 17.

LRU (Least Recently 1Jse
d) Circuit 21 executes logic for selecting candidates for page swapping.

Channel 26 controls data transfer between MS 25 and disk device 27.

The disk device 27 stores pages that have been paged out.

(Effects of the Invention) According to the present invention, the memory size suitable for the program is automatically set, and the overhead of paging in virtual memory and the activation frequency of the garbage collector are balanced, so that the overhead of both can be reduced. This results in improved processing efficiency and faster processing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the configuration of one embodiment of the invention, and FIG. 3 is an explanatory diagram of free space generated in virtual storage. In Figure 1, 1: CPU 2: First timer circuit 3: Second timer circuit 4: Ratio calculation circuit 5: Threshold register 6: Comparison circuit 7: Memory size register 8: Memory size increase/decrease circuit 9: Page table Control unit 10: page table

Claims (1)

[Claims] An information processing device including a virtual memory and a garbage collector, comprising: a first timer circuit (2) for measuring the entire execution time or the execution time excluding garbage collection processing of the garbage collector; A second timer circuit (3) that measures the execution time required for garbage collection processing of the collector, and a ratio calculation that calculates the ratio of the execution time required for garbage collection processing to the entire execution time or execution time other than garbage collection processing. a circuit (4), a threshold register (5) that holds a predetermined threshold for the ratio, a comparison circuit (6) that compares the threshold with the ratio calculated by the ratio calculation circuit (4), and a memory. The memory size register (7) is equipped with a memory size register (7) that holds the size, and a memory size increase/decrease circuit (8) that increases or decreases the value of the memory size register (7) based on the comparison result output of the comparison circuit (6). A variable memory size virtual storage system characterized in that the memory size of the virtual storage is increased or decreased by changing the usage range of a page table (10) according to an increase or decrease in the value of .