JPS6375962A - Multiprocessor communication equipment - Google Patents

Abstract

PURPOSE:To simplify a transmission processing, and to shorten the processing time, by sending the data to a communication processor corresponding to a transmission origin communication equipment stored in a memory means, when the data is transmitted to the transmission origin communication equipment. CONSTITUTION:When the communication processor 1 receives the data from an opposite communication equipment, the identifying means 2a of a processor 2 for processing identifies the communication processor 1 receiving the data corresponding to an opposite side communication equipment, that is the transmission origin communication equipment, and the memory means 2b stores an identified result. Afterwards, when the data is transmitted to the transmission origin communication equipment, the processor 2 for processing sends the data to the communication processor 1 corresponding to the transmission origin communication equipment stored in the memory means 2b, and the data is transmitted from the communication processor 1 to the transmission origin communication equipment. In such a way, it is possible to heighten universal applicability, to simplify the transmission processing, and to shorten the processing time.

Description

[Detailed Description of the Invention] [Summary] In a multiprocessor communication device, a transmission source communication device and a reception source communication processor of received data are stored, and when data is subsequently transmitted to the transmission source communication device, the reception source communication device is stored. By transmitting through the communication processor, the transmission process is simplified and the processing time is shortened.

[Industrial application field]

The present invention relates to a multiprocessor communication device, and more particularly to a method for selecting a data transmission route in a multiprocessor communication device.

[Prior art and problems to be solved by the invention]

With the expansion of communication networks, the capabilities of communication devices, which are the core of the network, are being expanded through multi-broadcasting.

By the way, in a multiprocessor communication device, there are cases where a transmission/reception link spans a plurality of processors. For this reason, several multiprocessor communication devices have been proposed in the past, each having its own data communication route selection method.

The first conventional device shown in FIG.
1 or communication processor ja22, and the data transmitting device 231 uses this memory 23.
It has a method of uniquely determining a data transmission route based on data stored in 2. In this case, since the data stored in the memory 232 differs depending on each multiprocessor communication device, there is a problem that the memory contents cannot be shared, and therefore the versatility is low.

In the second conventional device shown in FIG. 9, when the data transmission device 332 of the processing processor kb33 transmits data, the processor designation device 331 first sends data to the link management device 311 of the communication processor 1b31 or the communication processor j. It has a method of asking the link management device 321 of b32 whether or not the communication processor accommodates a link with the communication device to which the data is to be transmitted, and waiting for the answer to determine the data transmission route. ing. In this case, 1
Processor kb33 needs to inquire processor 1b31 or processor jb32 every time it sends data, which makes the sending process complicated and takes a long time, making it difficult to send large amounts of data. There is.

In the third conventional device shown in FIG. 10, the data transmitting device 431 of the processing processor ke43 always sends data to a predetermined communication processor, for example, the processor 1c41. Then, if the processor 1c41 does not accommodate a link with the communication device to which the data is transmitted, the processor 1e41 transmits the data to the processor jc41.
42, and processor jc42 sends the data. In this case, there is no problem when the processor 1c41 transmits data, but when the processor jc42 transmits data, the processing time increases by bypassing the processor 1c41, and as a result, it becomes difficult to transmit large amounts of data. There is a problem.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a multiprocessor communication device that is highly versatile, and that simplifies transmission processing and shortens processing time.

[Means for solving problems]

FIG. 1 is a principle block diagram of a multiprocessor communication device according to the present invention. In the figure, numeral 1 is a communication processor that transmits and receives data to and from a communication device on the other side, and a plurality of communication processors 1 are provided in the multiprocessor communication device.

2 is a processing processor that processes received data and transmitted data. This processing processor 2 is an identification means 2a.
and storage means 2b, and the identification means 2a identifies, from the received data, the plurality of communication devices that received the data corresponding to the source communication device among the plurality of communication devices of the other party that transmitted the data. The storage means 2b is for storing the reception source communication processor 1 corresponding to the transmission source communication device identified by the identification means 2a. It is.

[For production]

The communication processor 1 identifies the communication processor 1 that received the data corresponding to D from the other party's communication device, and the storage means 2b stores the identification result.

Thereafter, when transmitting data to the source communication device, the processing processor 2 uses the information stored in the storage means 2b.
Data is sent to the communication processor 1 corresponding to the source communication device, and the data is transmitted from this communication processor 1 to the source communication device.

〔Example〕

FIG. 2 is a block diagram of a multiprocessor communication device according to an embodiment of the present invention. In the figure, 11 is a communication processor i. This processor ill is the transmitting/receiving device 1
11 and an inter-processor communication device 112, and the transmitting/receiving device 111 communicates with other communication devices [1] via a link 14.
5.

12 is also a communication processor j similar to processor i, and this processor jL2 includes a transmitting/receiving device 112 and an inter-processor communication device 122 that are connected to another communication device group [17 via a link 16]. .

13 is a processing processor. This processor k1
3 is an inter-processor communication device 131, a Bromo-7 identification device 132 as the identification means 2a in FIG. 1, an inter-processor communication device 133, and a processor designation device 134.
, a memory 135 as the storage means 2b in FIG.
processor storage control device 136, transmission processing device 137,
It includes a reception processing device 138 and a memory 139 that stores billing data and the like.

Next, the operation of the above configuration will be explained with reference to the data flow chart shown in FIG. Furthermore, as shown in Fig. 4,
It is assumed that communication is performed with communication mA included in the group of other communication devices 115 (FIG. 2), and the link with the communication device A is accommodated in the processor ill.

First, the case where data is transmitted at the initial time will be explained. In this case, as shown in FIG.
Transmission is carried out through a stage (■) in which the data is sent from the processor j to a predetermined processor j, a stage (■) in which the data is transferred from the processor j to the processor i, and a stage (■) in which the data is transmitted from the processor i to the opposing communication device A. Complete.

To explain the above operation in more detail, the transmission processing device 137 of the processor k13 sends the transmission data read from the memory 139 and data indicating the communication device A (opposite communication device number to be described later) to the processor instruction device 134. Then, the processor specifying device 134 specifies the processor that accommodates the link with the opposite communication device from the address corresponding to the opposite communication device number of the processor identification information shown in FIG. 5 stored in the memory 135. but,
At the initial time, the opposite communication device and the processor are arbitrarily combined, so the processor specified by the processor identification information does not necessarily accommodate the link with the opposite communication device, and in this case, processor j It is specified. As a result, the transmission data is sent to the inter-processor communication device 123 of the processor 02 via the inter-processor communication device 133. The above is the above step (■).

Next, since processor j12 does not accommodate a link with communication device A, the transmission data is transferred from interprocessor communication device 122 to interprocessor communication device 112 of processor ill that accommodates that link. The above is the above step (■).

Then, the processor i11 transmits the transmission data transferred from the processor j12 to the communication fiA using the transmitting/receiving device 111.0 or more is the above step (2).

Next, a case will be described in which data is received from the ε-equipped WA.

First, communication device A sends data to processor i along with a bit representing communication device A (step ■).

Then, processor i applies processor i to the received data.
is sent to processor k with a bit representing
).

When the processor receives data, it performs data reception processing whose processing procedure is shown in FIG. First, step 6
At step 1, source processors corresponding to source communication devices are identified and stored. That is, the processor identification device 132 identifies the received data from the bits indicating the opposing communication device (in this case, A) and the processor (in this case, i), and the processor storage control device 136 identifies them from the memory. The processor number, i.e., i, is written in the address corresponding to the opposite communication device number of the processor identification information of No. 135. In other words, j is rewritten to i. Next, in step 62, reception processing is performed. That is, the reception processing device 138 processes the received data.

Next, a case will be described in which data is transmitted to communication device A after the data reception process described above is performed. In this case, data transmission processing is performed according to the procedure shown in FIG. First, in step 71, it is determined whether or not there is data to be transmitted. If the determination result is affirmative (YES), that is, if there is data to be transmitted, the process proceeds to step 72, and a destination processor is determined. This is determined by the processor designation device 134 by referring to the processor identification information stored in the memory 135. In this case, since the number representing processor i is written in the address of the opposing communication device number representing communication device A, processor i is determined as the destination processor. Next, the step knob 73 transfers the data to the processor determined in step 72, in this case processor i. That is, the transmission data is directly sent from the inter-processor communication device 131 to the processor ill without bypassing the processor 02 (step ■ in FIG. 2), and the data is sent from the processor i to the opposing communication device A. (stage ■). Note that if the determination result in step 71 is negative (No), the program stops.

〔Effect of the invention〕

As explained above, according to the multiprocessor communication device of the present invention, once data is received, the communication device that is the source of the data can easily determine which processor is capable of transmitting the data. Simplification and processing time can be reduced. Furthermore, since there is no need to store information regarding links in memory in advance, versatility is increased.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a block configuration diagram showing an embodiment of the present invention, Fig. 3 is a data flow chart, Fig. 4 is a system configuration diagram, and Fig. 5 is a processor identification information 6 is a flowchart of a data reception processing program executed in the present invention; FIG. 7 is a flowchart of a data reception processing program executed in the present invention; FIG. 8 is a block diagram showing a first conventional example; FIG. 9 is a block diagram showing the second conventional example, and FIG. 10 is a block diagram showing the third conventional example. DESCRIPTION OF SYMBOLS 1... Communication processor, 2... Processing processor, 2a... Identification means, 2b... Storage means, 1
32... Processor identification device, 134... Processor designation device, 135... Memory, 136... Processor storage control device. Figure 1: Block diagram of the principles of the present invention; Block configuration diagram showing an embodiment of the present invention; Figure 2: 1416 link processor 1; Processor J data flow chart; Figure 3: system configuration diagram; Figure 4: link processor Configuration diagram of identification information Fig. 5 Flowchart of RAM Ram flowchart 1/Fig. 6 Fig. 7 Block diagram showing the first conventional example Fig. 2 Block diagram showing conventional example u1

Claims (1)

[Claims] 1. A plurality of communication processors (1) that transmit and receive data with a plurality of communication devices on the other side, and one processing processor (1) that processes received data and transmitted data. 2)
In the multiprocessor communication device, the processing processor (2) extracts, from the received data, the data corresponding to the transmission source communication device among the plurality of communication devices on the other side that transmitted the data. Identification means (2a) for identifying the receiving source communication processor (1) among the plurality of communication processors (1) that received the communication;
and storage means (2b) for storing the receiving source communication processor (1) corresponding to the transmitting source communication device identified by the identifying means (2a), and transmitting data to the transmitting source communication device. A multiprocessor communication device characterized in that when transmitting data, the data is sent to the communication processor (1) stored in the storage means (2b) and corresponding to the transmission source communication device.