JPS6375785A - Display control system - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Output of a character pattern generator that generates character patterns based on character codes in a code memory and video
Input the output of the memory to the data modify circuit,
This is a display control method in which re-input data is calculated by a data modifying circuit, and the output of the data modifying circuit can be written back into the video memory.

[Industrial application field]

The present invention processes a character pattern generated based on a character code stored in a code memory and image information stored in a video memory by a data modification circuit, and outputs the data modification circuit. The present invention relates to a display control method that allows video data to be stored in video memory again.

[Conventional technology]

Conventionally, in order to display characters quickly, or because memory was very expensive and had to be used sparingly, a small code memory was prepared and the character code was stored there. The character pattern generator was moved according to the display timing, and the resulting pattern was projected onto the display in synchronization with the display timing.

Then, as memory became cheaper and there was a growing desire to process characters as images (so called bitmaps), processors read out corresponding character patterns from character pattern memory and stored them in video memory. A method has come to be adopted in which the character pattern is edited by storing it in an arbitrary position above.

[Problem to be solved] However, in the case of the bit map method, the transfer of pattern data must be completed before the display device scans one screen (it is necessary to complete the transfer of pattern data over many scans). (Rewriting pixels causes flickering), and as pixels become larger in capacity, processing time becomes more limited, and eventually it becomes necessary to dedicate the processor responsible for display control. There is.

The present invention was created in view of this point, and aims to reduce the display-related load on the processor and to store image information in an easy-to-handle format.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention. In the figure, 1 is a code memory, 2 is a timing generator, 3 is a memory gate circuit, 4 is a character pattern generator,
5 is a video memory, 6 is a command register, 7 is a latch, 8 is a data modification circuit, 9 is a display, and 10 is a parallel-to-serial conversion circuit.

A plurality of character codes are stored in the code memory l. The timing generator 2 supplies timing signals to each circuit. The image information sent from the processor (not shown) via the system bus and the output from the data modify circuit 8 are input to the memory gate circuit 3, and one of them is inputted according to an instruction signal. is selected and output. Character pattern generator 4 outputs character patterns corresponding to character codes output from character code 1. The output of the memory gate circuit 3 is input to the video memory 5. Commands sent from the processor via the system bus are input to the command register 6. The output of the video memory 5 is temporarily set in the latch 7. The output of the latch 7 and the output of the character pattern generator 4 are input to the data modifying circuit 8, and the data modifying circuit 8 calculates and outputs the re-input data. The parallel-to-serial conversion circuit 10 converts the parallel data from the data modifying circuit 8 into serial data, and sends the serial data to the display device 9.

〔Example〕

FIG. 2 is a block diagram of one embodiment of the present invention.

In the figure, 11 is a microprocessor, 12 and 13
14 represents a multiplexer, 14 represents a bus driver, and 15 represents a display control circuit. microprocessor 1
1 writes the character code to code memory 1,
Image information can be written to the bit map video memory 5 and to the command register 6. The multiplexer 12 is connected to the display control circuit 1
5 and the address output by the microprocessor 11 according to the instruction signal,
The selected address is given to the code memory 1. The multiplexer 13 selects either the address output from the display control circuit 15 (a concatenation of the memory address and the raster address) or the address output from the microprocessor 11 according to the instruction signal, and selects the address. This address is given to the video memory 5.

The bus driver 14 drives old data into the code memory 1. The display control circuit 15 is
It has internal memory address generator, timing generator, raster address generator, etc.

When a character code is stored in the code memory 1, at a predetermined timing by a timing generator, the data in the code memory 1 is read out, the pattern generator 4 is activated, and a character pattern is obtained. This pattern information is held until the next pattern is selected.

On the other hand, an output is obtained from the video memory 5 at approximately the same time as the output from the pattern generator 4, and since it is once latched, the output is immediately stopped. At this point, the output of the pattern generator 4, which is still valid, and the data from the video memory 5, which has been bordered once, are input to the data modifying circuit 8.

The data modify circuit 8 is a command register 6
Rewriting or overwriting is specified using various commands stored in the memory, and a modifier operation is performed for only one frame scanning period using an execution command. In actual use, a character code is set in the code memory 1 in advance, the modification work content is instructed in the command register 6, and finally an execution command is issued.

FIG. 3 is a timing chart for explaining the present invention in detail. Pattern generator output and video
The memory output is simultaneously input to the data modifying circuit 8. Data will be output from the data modify circuit 8 at the next timing, but at this point the memory
The gate circuit 3 selects and outputs the output of the modify circuit.

Therefore, reading/writing takes place during one memory cycle of the video memory 5.

FIG. 4 is a block diagram of one embodiment of a data modify circuit. In the same figure, 6 and 17 are OR circuits, 1
8 to 22 are AND circuits, and 23 is a latch. When the overwrite enable signal is on, the data modify circuit 8 outputs a superimposed output from the pattern generator and the video memory. When the pattern generator output priority signal is on, the pattern generator side output is
It is output from the modify circuit 8. The pattern generator output signal φ is one of the pattern generator outputs.
This is a signal that turns on when the word is O. Rewrite enable signal is on and pattern generator output φ
In this case, the video memory side output is output from the data modify circuit 8.

FIG. 5 is a diagram showing an example of the output of the data modify circuit. Assume that the output of the video memory before modification is something like the jonin side in Figure 5, and that the output of the pattern generator before modification is something like the upper cloth side in Figure 5. do. When the signal state is as shown in FIG. 4a, the image information as shown in FIG. 5a is output from the data modifying circuit 8, and when the signal state is as shown in FIG. Image information is output from the data modifying circuit 8, and if the signal state is as shown in FIG. 4C, the image information as shown in FIG.
It is output from the modify circuit 8.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, characters or mosaic patterns prepared in a pattern generator can be quickly rewritten with a few read/write operations, and characters can be rewritten as images. Since it can be treated as information, it can be easily reprocessed.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a block diagram of one embodiment of the invention, Fig. 3 is a timing chart for explaining the invention in detail, and Fig. 4 is a diagram of the data modification circuit. FIG. 5, a block diagram of one embodiment, is a diagram showing an example of the output of the data modifying circuit. ■...Code memory, 2...Timing generator, 3...Memory gate circuit, 4...Character pattern generator, 5...Video memory, 6...
...Command register, 7...Latch, 8...Data modify circuit, 9...Display, 10
... Parallel-serial conversion circuit, 11 ... Microprocessor, 12 and 13 ... Multiplexer, 14 ... Bus driver, 15 ... Display control circuit, 16 and 17 ...
・OR circuit, 18 to 22...AND circuit, 23・
··lunch.

Claims (1)

[Claims] A video memory (5) that stores display data that corresponds one-to-one with the screen on the display, and a code memory (5) that stores character codes corresponding to characters displayed on the screen.
1), a character pattern generator (4) that generates character patterns according to the contents of the code memory (1), and pattern data obtained from the character pattern generator (4) and video memory (5). data that is superimposed or rewritten with the pattern data that was created.
A modify circuit (8), a memory gate circuit (3) that switches between data from the data modify circuit (8) and data to be written directly from the system bus to the video memory (5), and a timing control for each part. It is equipped with a timing generator (2) that supplies a signal, a circuit (10) that transfers the output of a data modify circuit (8) to a display, and converts character information given as a code directly as code information or as image information. A display control method that is characterized by the ability to handle