JPS637537A - Recording medium inspecting device - Google Patents

Abstract

PURPOSE:To attain a various kinds of evaluation and analysis on errors, by providing a memory means which memorizes a write data, and a write control signal generating means which outputs a write control signal to the memory means, at an address designated by the counted value of a second counter means. CONSTITUTION:A memory means 11 which memorizes the write data consisting of an error pattern signal, and the count value of a first run length counter means 9, and a means which outputs the write control signal to the memory means, are provided at the address designated by the count value of a second address counter means 10, based on a write control signal, the inverse of WE. After completing the measurement of a test data, a data processing is performed. The count value of a second block in the write data recorded at each address of a RAM11, is arranged in a sequence of addresses according to the scale of a lateral axis, and when the block value of a first block is '1', a vacant part is generated by a corresponding length. In this way, it is possible to confirm visually an error part due to flaw, or dust on a disk at time of recording and reproduction, and to use it for various kinds of evaluation or analysis.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a recording medium inspection device, which uses data processing to determine the performance of a recording medium (position of errors on the recording medium, error distribution, etc.) and the performance of a recording/reproducing device ( optical system, servo system,
It evaluates and examines the electrical circuit, modulation method, quality of recorded data, etc.).

[Prior Art] Conventionally, a device for detecting an error occurrence position on a disk has been proposed in Japanese Utility Model Application Publication No. 61-21060. This error position detection device is equipped with a counter that generates position information by counting predetermined Glock pulses during one rotation of the disk, and the counter counts in synchronization with an error signal generated during the process of inspecting the disk. The value is stored in the storage means as error position information. In addition, in order to cope with fluctuations in disk rotation speed, the count value for one rotation is read each time, and the stored error position information (count value) is determined according to the size of the count value for one rotation.
This is to correct the location information and obtain correct location information.

[Problems to be Solved by the Invention] In the conventional error position detection device, the memory address for recording error information is determined by a counter that counts clock pulses, and each address has an error identification signal in response to the clock pulse. written. Therefore, the memory requires a large capacity, leading to an increase in cost. Furthermore, in order to cope with fluctuations in the disk rotation speed, it is necessary to read the count value for one rotation each time.

The present invention has been made in view of the above-mentioned points, and provides a disk-type recording medium inspection device that can record inspection data of a disk-type recording medium without requiring a large capacity memory. It is.

Furthermore, since the recording medium inspection device of the present invention uses a method of capturing all error pattern signals and disk reference position detection signals, by processing the data captured by this device with a computer, it is possible to determine the error position on the disk. You can check whether the error is occurring and know the distribution of errors. In addition, by plotting the distribution of solid burst error length (consecutive incorrect symbols) and EF run length (consecutive correct symbols), it is possible to determine whether errors occur randomly or in bursts. Various evaluations and considerations can be made, such as knowing whether this is the case.

[Means for solving the problem] In a recording medium inspection device that inspects a recording medium by recording and reproducing predetermined data on a recording medium and detecting errors that occur in the process, it is possible to use unit data of the data. , an error pattern generating means for detecting the presence or absence of a recording/reproduction error and generating an error pattern signal that takes a first or second state depending on whether or not the recording/reproduction error is detected; and a count pulse having the same cycle as the unit data. a count pulse generating means for generating a reference position of the recording medium; a position detecting means for outputting a reference position detection signal representing a reference position of the recording medium;
clear pulse generating means for outputting a clear pulse when the state of the error pattern signal is reversed and when the reference position detection signal is input; and the count.

a first counter means that counts with a pulse and clears the count value with the clear pulse; a second counter means that counts with the clear pulse; and a count value of the second counter means based on a write control signal. The error pattern signal and the first
A memory means for storing write data consisting of a count value of a counter means, and a write control signal generating means for outputting a write control signal to the memory means.

[Operation] The first counter means counts count pulses, and the count value indicates the number of consecutive EF silane or solid burst errors.

The second counter means counts the clear pulses, and the count value indicates the address of the memory means. The memory means records write data consisting of the error pattern signal and the count value of the first counter means at the address designated by the second counter means. The error pattern signal of this write data indicates the type of write data such as EF silane solid burst error, and the first
The count value of the counter means indicates the length.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a recording medium inspection device of the present invention;
2(a) to 2(c) are timing charts showing an example of the operation of the recording medium inspection apparatus shown in FIG. 1.

Reference numeral 1 denotes a recording system controller which outputs a data clock RDCK to the data generator 2 and controls the start, stop, etc. of the data series M s s q through a control line C 1 . 2 is a data generator that outputs a data sequence M seq to be recorded on the disk in synchronization with the data clock RDCK. It consists of an 8-bit symbol unit. The pattern of the data series M se q is shown below, and the data value of each symbol uses a hexadecimal value.

...000000000000 FF FF
FF FF FF MlM.

k-Start pattern→←- M, ・-・”・・Mn-□Mn 000000000
00000 ...... -Test pattern->End pattern example The above data series M seq has three or more consecutive data [00], followed by data [F F] of 5
A starting pattern indicated by consecutive times and a 20th order M sequence which is a pseudo-random sequence (period is 2”-1 bit)
It is formed from a test pattern shown by , and an end pattern shown by five consecutive data [00F. Further, the length of the test pattern is determined according to the recording time, and when the recording time is long, the same series is repeated.

3 indicates an EFM modulator, which performs EFM modulation by inputting the data clock RDCK from the recording system controller 1 and the data sequence M s eq of 8-bit symbols output from the data generator 2, respectively. R
A data sequence M of 14-bit symbols in synchronization with DCK,
Output Mseq.

4 indicates an optical recording/reproducing device, which records the data series M and Mseq output from the EFMFM modulator in one frame of 588
Recording is performed on a disk to be inspected (not shown) at a constant linear velocity (CLV control) according to the following format consisting of channel bits.

l 5ync+Sub code IDxlDiID
ii・”...=...lDi, 1Dizlk44 ch
annel bit4e-32X17 channel
bit-1-I Frame (588channel
el bit) - Each data entry in the above format - D32 is the data series M, Msaq each data (14
bit) plus extra bits (3 bits). This recording format is based on the compact disk (CD) format, and is mainly necessary for accurately operating CLV control during reproduction of the optical recording and reproducing bag-4.

Further, during reproduction, the optical recording/reproducing apparatus 4 outputs a disk reference position detection signal RSYNC of one pulse for each rotation of the disk to the reproduction system controller 8, which will be described later, by means of a position detection means (not shown). This position detection means can be realized, for example, by optically detecting a label affixed to the label portion of the disk to be inspected. In addition, if the disk drive method is a direct drive method, it is possible to obtain a signal from the motor, but the former is preferable in order to detect the error position of the disk. Device 4
Playback data M, PBD (14 bits) output from
EF to EFM demodulate the data into playback data PBD (8 bits)
It is an M demodulator.

6 is a data generator that outputs a data sequence M s e q in synchronization with the data clock PDCK output from the EFM demodulator 5;
q is the data sequence M s output from the data generator 2
It is the same as the test pattern of eq.

7 is reproduced data PBD output from the EFMFM demodulator in parallel in synchronization with the data clock PDCK;
This is a data comparator that compares the data series M s e q output in parallel from the data generator 6 symbol by symbol (8 bits), and when the reproduced data PBD and the data series M s e q are the same, “HI+double signal, if different, IF L I+double signal error pattern C
Output OMP.

8 is a playback system controller, 9 is a 16-bit run length counter, 10 is a 14-bit address counter, and 11 is 4
A random access memory (hereinafter abbreviated as RAMII) of K words (1 word = 16 bits) is shown.

The reproduction system controller 8 receives the data clock PDCK and reproduction data PBD output from the EFMFM demodulator, and detects a start pattern and an end pattern by reading the reproduction data PBD. The control line C2 controls the start and stop of the data series Mseq output from the data generator 6.

Control lines C3 and C are connected between the playback controller 8 and the run length counter 9, and between the address counter 10, respectively.
The playback system controller 8 outputs an initial reset signal, and the address counter 10 and run length counter 9 output an overflow detection signal.

The reproduction controller 8 also outputs the count clock ECK to the input terminal of the run length counter 9 and the clear signal CLR to the clear terminal of the run length counter 9 and the input terminal of the address counter 1o, respectively.

The count clock ECK is a signal that has the same period as the data clock PDCK and is delayed by a predetermined time, and is output during error pattern measurement. The clear signal CLR is output as a one-pulse pulse signal when the polarity of the error pattern GOMP is reversed or when an overflow of the run length counter 9 is detected, and as a two-pulse pulse signal when the reference position detection signal RSYNC is input, at the timings described later. be done.

The run length counter 9 successively counts the count clock ECK and always outputs this count data to the data input terminal of the RAMII, but repeats a 0 start every time the clear signal CLR is input. The negative address counter 10 sequentially counts the clear signal CLR and always outputs this count value as an address to the address input terminal of RAMII.

The RAM II inputs the count data of the run length counter 9 as well as the error pattern COMP and the polarity signal KS formed via the delay circuit 15 and the inverter INV16 as write data. And the playback controller 8
When the write control signal WE output from the address counter 1o becomes the II L 11 signal, write data is written to the address specified by the count data of the address counter 1o.

Note that RAM II outputs data at a specified address when the read control signal OE output from the reproduction system controller 8 is the NL11 signal. Also, write control signal W
E is an inverted pulse signal delayed by the same period as that of the data clock PDCK, and when the reference position detection signal R5YNC is input, a two-pulse inverted signal is superimposed at a timing to be described later.

The write data written to RAMII consists of a first block in which 16-bit data is a bit string, the most significant bit being data of the bit polarity signal KS, and a second block in which the lower 15 bits are count data of the run length counter 9. It consists of blocks. JF of the most significant bit of this bit string
Qll and u il+ are “L” of bit polarity signal KS.
11 and n HI+, respectively, and as described later,
It represents the data type of the lower 15 bits. Further, when all of the lower 15 bits are 0, it indicates a reference position detection signal regardless of the most significant bit.

Next, the order in which the count clock ECK, clear signal CLR, and write control signal WE are output from the reproduction system controller 8 during one cycle of the data clock PDCK will be explained.

1) When the polarities of the error patterns COMP are the same, the count clock ECK and the write control signal WE are output in this order.

2) When the polarity of the error patterns COM and P is reversed or when an overflow of the run length counter 9 is detected, the clear signal CLR, count clock ECK, and write control signal WE are
Output in this order.

3) When the reference position detection signal R8YNC is input, the clear signal CLR1 is additionally output twice in the order of the write control signal WE at timings described later.

12 is a computer, and the computer 12 and the reproduction system controller 8 are mutually controlled by a control line C1. The computer 12 receives the count data of the address counter 10, and reads the count value as the final value of the address at the end of measuring the test data. In addition, the computer 12 controls the read control signal ○E outputted from the reproduction system controller 8 through the control line C7 and the recontrol line C6 to read the data written in the RAM II.
Import data.

13 is a printer, and 14 is a display, which displays the data processing results of the data taken in by the computer 12.

Hereinafter, an example of these operations will be explained according to the timing charts of FIGS. 2(a) to 2(c).

Note that the numbers in parentheses indicate the order of operation, and the values in parentheses indicate data values.

The reproduced data PBD has its symbol value [D□ko~[Dnl
If the symbol ' is added to the symbol value, it is determined that an error has occurred, and the count values of the run length counter 9 and the address counter 1o are expressed in decimal notation.

(1) The data series recording data generator 2 is controlled by the recording system controller 1.
A data series M se q is output in the order of a start pattern, a test pattern, and an end pattern.

This data series Mseq is subjected to EFM modulation by the EFM modulator 3, and recorded on the disk to be inspected (not shown) in the above-described prescribed format by the optical recording/reproducing device 4K.

(2) Measurement of test data Next, the disk to be inspected on which the data sequence M seq has been recorded is reproduced by the optical recording/reproducing device 4K.

Reproduction data M and P output from the optical recording and reproducing device 4
The BD is EFM demodulated by the EFMtx modulator 5 and becomes reproduced data PBD.

The reproduction system controller 8 reproduces the reproduction data M, at the timing of the data clock PDCK output from the EFM demodulator 5.
The value of PBD is read and its starting pattern is detected. When the playback controller 8 detects the start pattern,
The data generator 6 is controlled by the control line C2, and the reproduction data PBD and the test pattern of the data sequence M seq outputted from the data generator 6 are synchronized. Thereafter, the reproduced data PBD and the data series M seq are output in synchronization with the data clock PDCK.

Furthermore, when the playback system controller 8 detects the start pattern of the playback data PBD, the control lines C1 and C4K are
The run length counter 9 and the address counter 10 are each initialized and their count values are cleared.6 The data comparator 7 compares the data values of the synchronized playback data PBD and the data series Mseq,
Determine errors in BD.

As shown in FIG. 2(a), the data comparator 7 outputs reproduced data PBD synchronized with the data clock PDCK<O>.
Symbol value [D] of <1> and data series Msaq<1
> symbol values [d eco are determined to be the same, and the error pattern GOMP<2> is set as the II H1+ signal. Next, the run length counter 9 uses the count clock ECK<3> outputted from the reproduction system controller 8 to set the count value 4> to 1]. RAMII is the write control signal W
With E<5>, the count value of address counter 10 (
(hereinafter referred to as address value) [Write data is written to the address of 0, but at this time, the most significant bit, which is the first block of write data, corresponds to the ''L I + times signal of the polarity signal KS [○] , and the value indicated by the lower 15 bits of the second block is the count value [1] of the run length counter 9.

Next, the data comparator 7 outputs the symbol value [D2'
It is determined that the symbol value [d2] of the data sequence Mseq<7> is different from the error pattern COMP<8>, and the error pattern
L” signal. Along with this, the reproduction system controller 8
A clear signal CLR<9> is output from the address counter 10, and the count value <10> of the run length counter 9 is cleared to [0], and the count value <11> of the address counter 10 becomes [1]. Next, the run length counter 9 has a count clock EC.
Due to K<12>, the count value <13> is set to [1]. Here, the error pattern G OMP 8> is I+L
The elapsed time from when the signal becomes ++ becomes the delay time set by the delay circuit 15, and the polarity signal KS<14> becomes II H.
``'' Signal 0th order RA Mll is write control signal WE
<15> sets the address value [1 address to the first
Write the write data of the value [1] of the block and the value [1] of the second block.

Next, the data comparator 7 uses the data clock PDCK<16>
Symbol value [D
,' is determined to be different from the symbol value [d1] of the data sequence M s e q (17>), and the error pattern COM
Let P<18> be the ITL11 signal. Therefore, the run length counter 9 sets its count value <20> to [2] based on the count clock ECK<19>. RAMII writes the write data of the first block value [1] and the second block value [2] to the address value [1 address] by the write control signal WE<21>, and then writes the write data. Update.

Next, the data comparator 7 uses the data clock PDCK22>
Symbol value [D
4 and the symbol value of the data sequence Mseq<23> [d4
] are determined to be the same, and the error pattern COMP<24> is set as an "H" signal.

A clear signal CLR<2 is output along with this polarity reversal.
5>, the count value 26 of the run length counter 9 is cleared to [O], and the count value 27 of the address counter IQ becomes 2. 28>, the count value 29> is set to [1]. Here, a predetermined time has elapsed since the polarity reversal of the error pattern COMP<24>, and the polarity signal KS<30> becomes the PtL11 signal. RAM11
is set to address value [2] by write control signal WE<31>.
] Write the write data of the first block value [0] and the second block value [1] to the address.

Next, the data comparator 7 uses the data clock PDCK32>
Symbol value [D
, ] and the symbol value [d,
] are determined to be the same, and the error pattern COMP<34> is signaled by It ) (I+ times).

Therefore, the run length counter 9 has a count clock ECK<3.
5>, the count value <36> is set to [2 pieces].

Similarly, the data comparator 7 uses the data clock PDCK<
38>, 44> are judged to be the same, and the run length counter 9 uses the count clock EC.
By K<41>, ku47>, the count value ku42>,
48> are set to [3 and [4], and the write control signal WE<
43>, 49>, the address value of RAMII is written to [2 addresses]. The values of the second block of write data are updated to [3] and [4].

Next, the data comparator 7 uses the data clock PDCK<50>
Symbol value [D
, ' ] and the symbol value [
d8 is judged to be different, and the error pattern COMP<5
2> is the II Ll+ signal. With the clear signal CLR<53> outputted in conjunction with this polarity reversal, the count value <54> of the run length counter 9 is cleared to [0], and the count value <55> of the address counter 10 becomes [0].
There will be 3 pieces. Next, the run length counter 9 changes the count value <57> to [1] using the count clock ECK<56>.
]. Here, a predetermined time has elapsed since the polarity of the error pattern COMP<52> was reversed, and the polarity signal KS<58> becomes the jlH1+ signal. RAM11 receives write control signal W
Due to E<59>, the first
Write the write data of the block value [1 piece, the value of the second block [1 piece].

As described above, the write data of the EF run length and the solid burst error length are sequentially written to RAMII.

Next, while counting the EF run length, the reference position detection signal R3Y
The case will be explained assuming that NC is input as shown in FIG. 2(b).

The data comparator 7 has a symbol value [D, ] of the reproduced data PBD<61> that is synchronized with the data clock PDCK<60>.
and the symbol value cd,] of the data series Msaq<61> are determined to be the same, and the error pattern COMP<62> is set to "H".
With the clear signal CLR<63> outputted in conjunction with this polarity inversion, the count value <64> of the run length counter 9 is cleared to [0], and the count value of the address counter 1o becomes <65>. becomes [4].

Next, run length counter 9 counts clock ECK66.
>, the count value 67> is set to [1]. Here, a predetermined time has passed since the polarity reversal of the error pattern COM P<62>, and the polarity signal KS<68> has changed to II.
The write control signal WE<
74> writes the write data of the first block value [0] and the second block value [1] to the address value [4].

Similarly, the data comparator 7 uses the data clock PDCK.
Both symbol values synchronized with <70> and (76>) are judged to be the same, and the run length counter 9 uses the count clock ECK.
<73>, 79> gives the count value 74>,
80> as [2], [3], and the RAMII address value [
The values of the second block of write data written to the four addresses are write control signals WE<75>, <81
> is updated to [2 pieces, [3 pieces].

Next, the data comparator 7 uses the data clock PDCK82>
The symbol value [D
symbol value [d
, , ] are judged to be the same, and the error pattern COMP<85
＞ is "HI+ times signal.

The playback system controller 8 takes in the reference position detection signal R5YNC output from the optical recording/playback device 4 at the timing of the fall of the write control signal WE. Then, while outputting the next count clock ECK, the clear signal CLR,
，? Two pulse signals are output alternately in the order of the input control signal WE, but the output timing of the first clear signal is set to match the timing of the clear signal output when the polarity of the error pattern COMP is reversed. There is.

Therefore, when the reference position detection signal 5YNC is taken in at the falling edge of the write control signal WE<81>, the count value <86> is cleared by the first pulse clear signal CLR<85> and becomes [01], and the address The count value of the counter 10 becomes [5]. RAMII is the write control signal W output after the clear signal CLR<85>
Due to E<88>, the first
The write data of block value [0] + second block value [0] is written. Then, by the second pulse clear signal CLR<89>, the count value <90> of the run length counter 9 is cleared again to [0], and the count value <91> of the address counter 10 becomes [6].

RAMII is set to the address value [6] by the write control signal WE<92> output after the clear signal CLR<89>.
The write data of the value [0] of the first block and the value [0] of the second block are written to this address. Then, the run length counter 9 is controlled by the count clock ECK<93>.
The count value 94> is set to [1].

RAMII writes the write data of the first block value [0] and the second block value [1 piece] again to the address of the count value [6] of the address counter 1o by the write control signal WE<95>. .

Thereafter, write data is written in the same manner, and until the count clock ECK<114> is output, the RAM is
The value of the second block of write data written to the address value [6] of II is [4].

Next, a case will be described assuming that EF silanes continue and the lower 15 bits of the run length counter 9 overflow (count value [32767]) as shown in FIG. 2(C).

The data comparator 7 detects the symbol value CD of the reproduced data PBD<115> which is synchronized with the data clock PDCK<114>.
,, the symbol value of the data sequence Mseq<115> [
clig] are the same, and the error pattern COMP<
116> is the It HTt signal. Since EF silane continues thereafter, the data comparator 7 continues to judge both data to be the same.

Then, at the stage when the write control signal WE<123> is output, the value of the second block of write data written to the address value [6] of RAMII is [3].
2766].

Furthermore, the data comparator 7 has a data blocker PDCK<12
Symbol value [D 327 ? of playback data PBD<125> synchronized with 4> □Co and data series Mseq<125
> are judged to be the same, and the error pattern GOMP<126> is set as the rJ H" signal.
7>, the count value <128> is set to [32767
Let's say ko. At this point, the run length counter 9 outputs an overflow detection signal to the reproduction system controller 8. When the reproduction system controller 8 receives this overflow detection signal, it outputs the clear signal CLR at the output timing of the clear signal that is output when the polarity of the error pattern signal COMP is reversed.
Outputs <133>. RAM11 receives write control signal W
Due to E<129>, the first block value [○] and the second block value [:32] are assigned to the address value [6].
767] write data.

Next, the data comparator 7 outputs a data clock PDCK<130.
The symbol value CD, □77,] of the reproduced data PBD<131> synchronized with Here, the count value <1.34> of the run length counter 9 is cleared to [01] by the clear signal CLR<133> caused by the overflow detection of the run length counter 9 described above, and the count value of the address counter 1o is <135> becomes [7 pieces.Next, the run length counter 9 changes its count value <137> by the count clock E:CK<136>.
> is [1]. Rlbill is the write control signal WE
<138> writes the write data of the first block value [○] and the second block value [1 piece] to the address of the address value [7].

Similarly, the data comparator 7 uses the data clock PDCK<
Both symbol values synchronized with 139>, <145>, and <151> are judged to be the same, and the value of the second block of write data written to the RAMII address value [7] is [2]. , [3 pieces, [4] are updated.

As described above, the test data is compared sequentially, and RAMII
records write data using the bit string display method of the present invention. Then, the reproduction system controller 8 outputs the reproduction data P.
When the end pattern of the BD is detected, the test data measurement is ended.

Table 1 shows the contents of the write data recorded in RAMII in the above operation example.

Note that the data value of address [7] [oooo.

00000000100] is not necessarily the final value,
For example, if the next reproduced data P BD [Dzz7-3 and the data series M s a CZ [dizt*il] are the same, they will be increased.

As shown in Table 1, each address in the RAM 11 has an EF run length of 1 symbol, a solid burst error length of 2 symbols, and an EF run length of 4 symbols after the start of test data measurement.
symbol, solid burst error length is 1 symbol, E
F run length is 3 symbols, reference position detection signal, EF run length is 32767 symbols, EF run length is 4 symbols, etc.
. . . and the inspection results of the recording medium are sequentially recorded.

(3) Data processing When the test data measurement is completed, the computer 12
It imports AMII data and processes the data using various programs.

The computer 12 reads the count data of the address counter 10 to know the final value of the used address of RAM II. Next, the computer 12 sequentially specifies addresses from 0 to the final value using a required program,
In addition, the read control signal OE output from the reproduction system controller 8 is set to an "L" signal at the required timing, and the RAM
The data recorded in II is read and taken into internal RAM (not shown). Next, the computer 12 processes the data using a required evaluation program, and displays the results on the printer 13 and display 14K.

3 and 4 display actual measurement results, and the measurement data at that time is as follows.

Disc: Write once optical disc Recording laser power: 4.8 (mW) Reproduction laser power: 0.3 (mW) Linear velocity:
1.8 (m/s) measurement time: 59
(sec) Total number of data: 4096 Total number of symbols: 14046359 Number of incorrect resymbols: 2896 Symbol error rate: 2.06 D-04 reference position detection signal = 591 In Figure 3 (a), the horizontal axis is the number of symbols and the vertical axis is the track This figure shows the error distribution on the disk under the following conditions.

1) Arrange the count values of the second block of write data recorded at each address of RAMII in address order from left to right according to the scale of the horizontal axis.

2) If the value of the first block of write data is [0, that is, when the second count value indicates the EF run length, the corresponding length is printed in black, and the value of the first block is [0]. In the case of one block, that is, when the count value of the second block indicates the burst error length, the corresponding length is left blank.

3) When the value of the second block of write data is the reference position detection signal of [01], move to the next track.

By displaying under the above conditions, scratches on the disc,
You can visually confirm error areas during recording and playback due to dust, etc. Furthermore, by comparing the number of symbols for each track (the position of the right end on the graph), the CLV control state of the optical recording/reproducing device 4 can be determined.

FIG. 3(b) shows the horizontal axis of FIG. 3(a) as the rotation angle of the disk. According to this display method, the error position and its size can be accurately detected from the number of tracks and the angle. Can be done.

FIGS. 4A and 4B show an EF run length distribution and a solid burst error length distribution, respectively, with the horizontal axis representing the number of symbols and the vertical axis representing the number of occurrences.

Further, solid lines A and B in FIG. 1 are calculated distributions when errors occur randomly. In the example shown in FIG. 4, there is a large deviation from this solid line, and it can be seen that many burst-like errors occur.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can take various forms.

For example, as shown in FIG. 5, the polarity signal KS of FIG. 2(a)
It is also possible to shift the following operation timing by Δt.

Also, in this case, the number of times the write control signal WE is output can be reduced. In other words, if the configuration is such that the write control signal WE is output after detecting the polarity reversal of the error pattern GOMP, the write control signal WE can be output when the polarity reversal is not detected without changing the write data that is finally stored in RAM II. WE (<18>, <34 in Figure 5
>, <4o>, <46>) can be omitted.

In the above embodiment, the error pattern signal GOMP is detected by symbol-by-symbol comparison of the reproduced data PBD and the data sequence M seq, but it can also be detected by bit-by-bit comparison or by using an error correction encoder or decoder. It is also possible to detect this by detecting a dropout of the reproduced signal. Furthermore, although a pseudo-random sequence is used as the test pattern, a fixed sequence may also be used.

Furthermore, although the optical recording and reproducing device 4 is assumed to perform recording and reproducing on a disk-type recording medium, it is not related to the format of the recording medium, such as a card-type recording medium, and the recording and reproducing method is not limited to optical. , magnetically, etc.

Furthermore, when recording and reproducing the test disk, it is also possible to change the modulation method and format method, and to use an error correction encoder and decoder.

[Effects of the Invention] As described above, according to the apparatus of the present invention, it is possible to provide a recording medium inspection apparatus that can detect error information in recording and reproduction without requiring a large amount of memory.

Furthermore, since the recording medium inspection device of the present invention takes a method of capturing all error pattern signals and reference position detection signals, a computer processes the data captured by the device,
By plotting, you can see how errors occur on the disk and understand the distribution of errors. Furthermore, by similarly plotting the EF Clan solid burst distribution, it can be used for various evaluations and studies, such as knowing whether errors occur randomly or on bursts.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing an embodiment of a recording medium inspection device according to the present invention, and FIGS.
Timing charts showing an example of the operation of the recording medium inspection device shown in FIGS. 3(a) and 4(b) and FIG. 4(a),
(b) is a diagram showing a display example of the recording medium inspection apparatus shown in FIG. 1; DESCRIPTION OF SYMBOLS 1... Recording system controller, 2.6... Data generator, 3... Modulator, 4... Optical recording/reproducing device, 5
... Demodulator, 7... Data comparator, 8... Reproduction system controller, 9... Run length counter, 10... Address counter, 11... RAM, 12... Computer, 13 ...Printer, 14...Display, 15...Delay circuit, 16...Inverter INV. Procedural amendment (voluntary) 1. Display of the case Patent Application No. 151028 of 1985 2, Name of the invention Recording medium inspection device 3, Person making the amendment Relationship to the case Patent applicant address 1-153 Suzuki-cho, Kodaira-shi, Tokyo 187
(0423) 42-14605, Contents of amendment (1) "Disk type" on page 5, line 16 of the specification is deleted. (2) Delete "disk type" on page 5, line 18 of the specification. (3) Delete "by control line C3" in the first line of page 17 of the specification. (4) rSYNCJ on page 27, line 8 of the specification
Correct to SYNCノ.

Claims (7)

[Claims] (1) In a recording medium inspection device that inspects a recording medium by recording and reproducing predetermined data on the recording medium and detecting errors that occur in the process, the presence or absence of recording and reproduction errors is determined using unit data of the data. an error pattern generating means for generating an error pattern signal that detects the recording/reproducing error and takes a first and second state depending on whether or not the recording/reproducing error is detected; and a count pulse generating means for generating a count pulse having the same cycle as the unit data. and position detection means for outputting a reference position detection signal representing the reference position of the recording medium; clear pulse generation means for outputting a clear pulse when the state of the error pattern signal is reversed and when the reference position detection signal is input; a first counter means that counts with a pulse and clears the count value with the clear pulse; a second counter means that counts with the clear pulse; and a count value of the second counter means based on a write control signal. A memory means for storing write data consisting of the error pattern signal and the count value of the first counter means at a specified address; and a write control signal generating means for outputting a write control signal to the memory means. A recording medium inspection device characterized by: (2) The error pattern generation means includes a demodulator 5, a data generator 6, a data comparator 7, and a pattern synchronization control means. Claim 1, characterized in that the data sequence Mseq output from the generator 6 is synchronously controlled, and the data comparator 7 compares the reproduced data PBD and the data sequence Mseq symbol by symbol. Recording media inspection device. (3) A patent characterized in that the data comparator 7 outputs an error pattern signal that becomes an "H" signal when the reproduced data PBD and the data sequence Mseq are the same, and becomes an "L" signal when they are different. A recording medium inspection device according to claim 2. (4) The recording medium inspection apparatus according to claim 1, wherein the first counter means is constituted by a 16-bit counter. (5) The memory means consists of four words each consisting of 16 bits.
2. A recording medium inspection device according to claim 1, characterized in that the recording medium inspection device is constituted by a random access memory of K words. (6) The most significant bit of the write data in the memory means is the error pattern signal COMP via the delay circuit 15.
The recording medium inspection apparatus according to claims 3, 4, and 5, wherein the lower 15 bits are the count value of the run length counter 9. (7) The recording medium inspection apparatus according to claim 1, wherein the count pulse generation means, the clear pulse generation means, and the write control signal generation means are constituted by a reproduction system controller 8.