JPS6374381A - Digital data converting system - Google Patents

Abstract

PURPOSE:To connect data digitally without passing through a digital-analog, analog-digital conversion route by providing data equivalent to that sampled at clocks integer times clocks of frequency 4 fsc by inserted interpolation. CONSTITUTION:An inserted filter 41a prepares inserted data using sampling data that varies in the direction of time. Sample data nearest to the sample position of clocks frequency 910 fh phase locked with horizontal frequency fh is selected by a selector circuit 42a. The selected sample data are stored in a memory 43a of the next stage. Stored image data are read out at clocks in frequency 4 fsc from the memory 43a, and supplied to a scanning line interpolation circuit 35. Thus, unification can be made smoothly without passing through a digitalanalog converter and an analog-digital converter. The scale of the circuit can be made small and deterioration of signals can by prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a digital data conversion method effective for demodulating a television signal by digital processing.

(Prior Art) In recent years, technology for digitally processing video signals inside television receivers has been developed.

The reason for this is that in the case of analog signal processing, the signal processing circuit can be made into a single-chip LSI (Large Scale Integrated Circuit), but many peripheral parts of the LSI are required, and there are still adjustment parts left, which reduces the cost. There are limits to this. In order to further improve the image quality, it is necessary to use memory to delay the signal and various filter operations, but digital processing provides much more accurate and stable processing than analog processing.

The signal processing section for which digitization is effective is a section that separates and demodulates a composite color video signal into a luminance signal and a chromaticity signal. In Japan, broadcasting is carried out using the NTSC system, so this will be used as an example in the following explanation.

FIG. 9 shows a system for demodulating an NTSC composite color video signal in which a chromaticity signal is multiplexed with a luminance signal. NTS
In the C method, the chrominance signal is quadrature modulated with a chrominance subcarrier of frequency fsc.

The fsc color subcarrier has a phase-inverted relationship for each line (scanning line), and by taking the difference between the front and rear scanning lines, the modulation signal can be separated from the composite color video signal, and this can be further separated into the fsc color subcarrier. The color signal is demodulated by synchronous detection using the subcarrier.

When a composite color video signal is supplied to the digital comb filter 11 of FIG. 9, a modulated color signal is obtained at its output. The comb filter 11 consists of a one horizontal period (hereinafter referred to as IH) delay circuit 12.13 and an adder 14.
By utilizing the fact that the frequency positions of the spectra of the luminance signal component and the chromaticity signal component shown in the figure are different from each other, the modulated color signal can be separated and extracted. This modulated color signal is supplied to a bandpass filter 15 and extracted as a modulated color signal of a predetermined band. The bandpass filter 15 includes one-clock delay circuits 16 and 17 and an adder 18, and removes the low band components extracted by the comb filter 11. The chromaticity signal obtained in this way is as shown in FIG.
When the NTSC signal is sampled with a 4 fsc clock and is sampled with the phase aligned with the {circle around (2)} axis, the sample data has l-axis components and Q-axis components arranged alternately. This signal is supplied to the synchronous detector 19 and alternately
If the %Q component is extracted, it means that synchronous detection has been performed, and a color signal can be obtained.

Generally, in order to demodulate a signal that has been orthogonally modulated, the carrier's S
A demodulated output can be obtained by multiplying the IN component and the CO8 component, but if sampling is performed digitally using a 4 fsc clock, the demodulated output can be obtained by simple filter processing. Therefore, in the system that obtains the demodulated output of the I and Q axis components described above, 4fsc
The sampling process using the clock is very important.

Furthermore, when color video signals are digitally processed, it is advantageous that scanning line interpolation processing can be performed. NTS
The C method uses a 2:1 interlace method. Interlacing thins out the scanning lines of one image before transmitting it, and is useful for compressing the transmission band, but on the other hand, it is a cause of image quality deterioration called ink-lace failure. A typical deterioration phenomenon is line flicker. This is a phenomenon in which the image appears to wobble vertically when it is a still image, but this can be eliminated by performing scanning line interpolation. In other words, the jitter can be eliminated by interpolating and reproducing the thinned out scanning lines. A two-dimensional or three-dimensional filter is required as a means for scanning line interpolation, which is difficult to do with analog technology, but it is relatively simple to do it digitally.

FIG. 12 and FIG. 13 are diagrams shown to explain the scanning line interpolation process. The scanning lines of the first field transmitted in an interlaced manner are shown by solid lines, and the scanning lines of the second field are shown by dotted lines. When performing interpolation, the scanning lines L1 and L2 before and after are used to create a scanning line L3 between them, doubling the number of scanning lines. The scanning line signal obtained in this manner is displayed by scanning the screen at twice the normal frequency, thereby improving the image quality. Although a line memory is required to perform the above-described scanning line interpolation, the interpolation process can be achieved relatively easily by digital processing.

Now, let us consider the clock when performing scanning line interpolation by digital processing. FIG. 14 shows the first scanning line L1 and the second scanning line L2. To perform interpolation using such scan lines, both scan lines L
When looking at L and L2 in the vertical direction, it can be understood that it is better to have sampling points at the same horizontal position.

However, for example, a home video tape recorder (hereinafter referred to as VT)
If you look at the signal reproduced from the R (referred to as R), there is often jitter in the horizontal synchronization. That is, as in the synchronization signal HD in FIG. 14, a shift may occur in the time axis direction. This is because mechanical factors in the rotation system of the VTR, expansion and contraction of the tape itself, etc. cause time axis fluctuations in the reproduced signal. The reason why images reproduced by such signals look normal in conventional television receivers is that the horizontal deflection circuit causes the cathode ray tube to perform horizontal scanning in automatic synchronization with the horizontal synchronizing signal. In other words, horizontal deflection scanning is performed following the horizontal synchronization signal.

However, if a signal with time-axis fluctuations is sampled as in the example in Figure 14 using something very stable, such as an fsc clock generated by a crystal oscillator, the sample position will shift line by line, and the vertical correlation will Correct interpolation cannot be expected. This phenomenon will be explained with reference to FIG.

Now, the scanning line signal Lll in the figure is a signal without jitter, the scanning line signal L12 is a signal with jitter, and the circled point is 4f s.
The sampling point is determined by the c clock.

When sampling with 4 fsc clocks, in the case of an NTSC video signal, the number of clocks required to sample the signal of one horizontal period is 910. However, the jittered scanning line signal LL2 (this example is shown as a signal with a shortened signal period) is sampled with fewer than 910 signals, so
The number of data will be 910 or less and will be stored in the memory. When scanning line interpolation is performed using data sampled in this way and data obtained by sampling a signal with no jitter, such as scanning line signal Lll, interpolation as shown in interpolated scanning line signal L13 is generated. data, and the signal waveform is no longer normal.

In order to eliminate the above-described defects in interpolation, it is necessary to ensure that 910 clocks exist within one horizontal period. For this purpose, it is necessary to use a clock generation circuit with a frequency of 910fh (fh is the horizontal frequency) and to improve the oscillation frequency of this circuit so that it follows the horizontal synchronization signal. FIG. 16 shows the sampling position and the interpolated scanning line signal L14 when the sampling clock frequencies of the scanning line signal Lll and the scanning line signal L12 change in accordance with the horizontal synchronizing signal.

(Problems to be Solved by the Invention) As explained in FIGS. 9 to 11, demodulation of color signals requires a clock with a frequency of 4 fsc, and the scanning line explained in FIGS. 910fh for interpolation processing
A clock with a frequency of Therefore, in order to create a system in which both color demodulation and scanning line interpolation are performed digitally, it is necessary to configure independent digital processing units depending on the difference in clock frequency. For example, there is a system as shown in FIG. 170. In FIG. 17, first, an NTSC system composite color video signal is input to an analog-to-digital converter 22 via an input terminal 21, and is converted into a digital signal. This digital video signal is manually input to the luminance/chromaticity demodulation circuit 23. The luminance/chromaticity demodulation circuit 23 demodulates the I-axis component and the Q-axis component as well as the luminance signal component Y, as explained in FIG. Next, the ■-axis component, Q-axis component, and luminance signal component Y are supplied to the digital-to-analog converter 24. This digital-to-analog converter 24 and the previous analog-to-digital converter 22,
The luminance/chromaticity demodulation circuit 23 is a clock system with a frequency of 4 fsc. Next, each demodulated signal is converted back into an analog
The signals are input to the digital converter 25 and converted into digital signals. The signal is then input to the scanning line interpolation circuit 26, where it is subjected to scanning line interpolation. Each scanning line interpolated signal is input to the digital-to-analog converter 27, converted into an analog signal, and supplied to the color picture tube side. The analog/digital converter 25, scanning line interpolation circuit 26, and analog/digital converter 27 are a clock system with a frequency of 910fh.

If a system is created in which both color demodulation and scanning line interpolation are performed in a series of processes in this way, a digital-to-analog converter 24 and an analog-to-digital converter 25 with different clock frequencies will be required, which will increase the cost. Furthermore, if digital-to-analog conversion and analog-to-digital conversion are performed continuously, the signal may be degraded. Furthermore, the brightness, ■
Three circuits for the axis and Q-axis components are required, which increases the price.

Therefore, in this invention, when processing circuits that require clocks of two different frequencies are connected in series as described above,
The purpose of the present invention is to provide a digital data conversion method that can be digitally combined without going through a digital-to-analog or analog-to-digital conversion processing path, which can reduce costs and reduce the causes of signal deterioration. shall be.

[Structure of the Invention (Means for Solving Problems) In this invention, in order to achieve the above object, a clock with a frequency of 4fsc, which is convenient for separation demodulation, is used on the luminance/chromaticity demodulation side. By interpolating the sampled data in the interpolation filter section, data equivalent to sampling with a clock that is an integer multiple of the sampled data is prepared in advance,
On the other hand, on the interpolation side, the interpolation process is performed using the 910fh clock, but when selecting the data to be used for interpolation from among the data equivalent to the data sampled with the integer multiple clock, the 910fh clock is used. The above objective is achieved by selecting the closest data.

(Operation) As mentioned above, data loss is eliminated by preparing data equivalent to sampling with a clock that is an integral multiple of the clock frequency of 4fsc by interpolation, and 910fh is obtained from the data prepared in this way. By selecting data close to the sampling position of the clock, even if the time axis on the input side fluctuates, when interpolating data between scanning lines, it is possible to prevent a temporal position shift between interpolated data. That's what I do.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which an analog composite color video signal is supplied to an input section 31, and this signal is converted into a digital signal by an analog/digital converter 32. This digital signal is input to the luminance/chromaticity demodulation circuit 33 and is separated and demodulated into a luminance signal component Yl, an I-axis signal component 11, and a Q-axis signal component Q1. These signal components are supplied to the digital-to-digital converter 34, which is a feature of the present invention.

The digital-to-digital converter 34 includes interpolation filters 41 a and 4 l b that interpolate each digital signal.

41c, and each interpolation filter 41a, 41b.

41c, and 9 of the outputs of the interpolation filter
A selection circuit 42a selects data closest to the sampling position of the 10fh clock.

42b, 42c, and each selection circuit 42a, 42b.

42c, and the output of each selection circuit is connected to 910.
It has a memory 43 that stores data with a clock of fh and reads out with a clock of 4fsc.

The digital signal output from the digital-to-digital converter section 1- is input to the scanning line interpolation circuit 35, interpolation of the scanning lines is performed, and the signal is input to the digital-to-analog converter 36. An analog luminance signal from this digital-to-analog converter 36, an I-axis signal component.

The Q-axis signal component is supplied to the picture tube drive circuit at the next stage.

The present invention is characterized by the digital-to-digital conversion section 34, and the operation of this section will be explained in principle below.

FIG. 2 representatively shows one system of the digital-to-digital converter shown in FIG. The interpolation filter 41a has
Sample data of a frequency of 4 fsc, which is indicated by a circle in FIG. 3, is supplied. The interpolation filter 41a creates interpolation data indicated by a triangle mark using sampling data that comes and goes before and after in the time direction. The amount of data obtained by this is equivalently 2
This is the same as sampling at twice the sampling frequency. Furthermore, this data is interpolated to create data at the position indicated by the X mark in the figure. The amount of data in this case is the same as if the signal were equivalently sampled at four times the sampling frequency. To perform interpolation in this way, for example, a delay circuit 50 as shown in FIG.
A coefficient unit 5 that multiplies each delay element 501 to 50n in the
21 to 52n, and a synthesis circuit 53 that synthesizes the outputs of the coefficient multipliers 521 to 52n.

The data prepared as described above is supplied to the selection circuit 42a. In this selection circuit 42a, sample data closest to the sample position of a clock having a frequency of 910fh that is phase synchronized with the horizontal frequency fh is selected, and this selected sample data is stored in the next stage memory 43a.

When selected in this way, as shown in Fig. 4, the video signal V
Even if D4 is jittered, the number of samples of video data for one horizontal period stored in the memory 43a will always be 910, and even though there are 910 samples, unnecessary portions of samples will be stored in the memory 43a. Contains no data. In other words, data distribution is obtained by sampling data for one horizontal period of a video signal in which jitter has occurred at equal intervals.

The video data stored as described above is read out from the memory 43a using a clock having a frequency of 4fsc, and is supplied to the scanning line interpolation circuit 35. Since the signal processed according to the present invention undergoes jitter correction in the digital converter 34, when looking at the data array in the vertical direction, the vertical correlation is maintained well.

FIG. 6 shows an example of the aforementioned selection circuit 42a in more detail, and FIG. 7 shows a time chart of the circuit shown in FIG.

In FIG. 6, DFFI to DFFIO are D-type flip-flop circuits (hereinafter referred to as flip-flop circuits), and flip-flop circuits DFFI, DFF2
, DFF3, the data of the circle mark position, the data of the X mark position, and the data of the triangular mark position described above are supplied in parallel, respectively. Here, the flip-flop circuit DFF1 is driven by an inverted clock of the 4fsc frequency clock, and the flip-flop circuit DFF2 is driven by an 8fsc clock.
Driven by an inverted clock of the sc frequency clock,
The flip-flop circuit DFF3 is driven by a clock having a frequency of 4 fsc. In this case, the data at the circle mark position,
The data at the mark position and the data at the triangular mark position are supplied in a staggered manner so that the data switching points do not occur at the same time, as shown in the time chart.

Each output data of flip-flop circuits DFFI, DFF2, and DFF3 is sent to flip-flop circuit DFF4.
．． DFF5. It is supplied to DFF6. This flip-flop circuit DFF4°DFF5. The DFF6 is driven by a 910fh clock phase-synchronized with the horizontal synchronization signal.

And this flip-flop circuit DFF4°DFF5.
The output data of DFF6 is sent to AND circuits 61 and 6, respectively.
2.63 is supplied to each one input terminal. The AND circuits 61, 62, 63 ($) select any one data according to the control signal from the code converter 66 and supply it to the flip-flop DFFIO via the OR circuit 64. The selection in .63 is 91
The data closest to the 0fh clock sampling position is selected, and the selection control signal is created as follows.

Flip-flop circuit DFF7. DFF8° and DFF9 each have an inverted clock of the 4fsc clock and an 8f clock.
An inverted clock of the sc clock.

A 4fsc clock is provided as a data input. And these flip-flop circuits DFF7°DFF8.
The DFF9 is driven by a 910fh clock phase-synchronized with the horizontal synchronization signal.

This means that the data closest to the sampling position of the clock with a frequency of 910 fh is 4 f sc.

Detection is performed using 8fsc and 4fsc clocks. In other words, flip-flop circuits DFFl, DFF
2. DFF3 also has 4fsc and 8fsc.

Since it is driven by a clock of 4 fsc, by sampling this clock with a clock of 910 fh, data output can be obtained from the flip-flop circuit with matching timing. flip-flop circuit DFF
7. DFF8. The output data of the DFF 9 is supplied to a code converter 66. This code converter 66 includes an exclusive OR circuit 67, AND circuits 68, 69, and a negative input OR circuit 70. The outputs of the AND circuits 68 and 69 are supplied to the other inputs of the AND circuits 61 and 62, and the output of the negative input OR circuit 70 is supplied to the other input of the AND circuit 62.

The conversion table of the code converter 66 described above is expressed as shown in FIG. An example of data selection will be explained with reference to FIGS. 6 and 7. At time t1, the output C of the flip-flop circuit DFF9 is "1m", and the outputs a and b of the other flip-flop circuits DFF7 and DFF8 are o'.

In this case, the output of the negative input OR circuit 70 becomes "1°," and the data at the sample position marked with X is selected. Time t2
Now, flip-flop circuits DFF7, DFF8 . DF
Outputs a, b, and c of F9 become "0, 1.1". In this case, the data at the sample position indicated by the triangle mark is selected. In this way, data in a stable state near the sample position of the frequency of 910 fh is selected and supplied to the next stage scanning line interpolation circuit.

[Effects of the Invention] As described above, according to the present invention, data processing circuits with different clock frequencies can be smoothly integrated without passing a digital-to-analog converter or an analog-to-digital converter in between. This makes it possible to provide a digital data conversion method that is effective in reducing circuit scale and preventing signal deterioration.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, an explanatory diagram of S-, the second diagram is a diagram showing an example of the interpolation filter shown in FIG. 2, and FIG. 6 is a diagram showing the selection of FIG. 2. Figure 7 is a diagram showing an example of the circuit, Figure 7 is a time chart shown in the operation explanation of the circuit in Figure 6, Figure 8 is a diagram showing a conversion table of the code conversion circuit in Figure 6, Figure 9 is a diagram showing brightness and color. A configuration explanatory diagram showing a degree demodulation circuit,
Fig. 10 is a diagram showing the frequency spectrum of the television signal, Fig. 11 is a diagram showing the demodulated output of the chromaticity signal, and Fig. 12 is a diagram showing the demodulated output of the chromaticity signal.
13 is an explanatory diagram of scanning line interpolation processing, FIG. 14 is an explanatory diagram of television signal jitter, and FIG. 15 is a diagram for explaining the jitter of a television signal. FIG. 16 is a diagram for explaining time axis correction when scanning line interpolation is performed. FIG. 17 is a conventional digital television signal processing circuit. FIG. 32... Analog-to-digital converter, 33... Luminance/chromaticity demodulation circuit, 34... Digital-to-digital converter, 35... Scanning line interpolation circuit, 36... Digital-to-analog converter, 41a to 41c... interpolation filter, 4
2a to 42c... selection circuit, 43a to 43c... memory. Applicant's representative Patent attorney Takehiko Suzue 4fsc L-tooooooo. Sample data 8fccL-to o Δ ○ Δ o Δ o
Δ ○ Δ Ochi9 16fscL-to oxΔxOXΔ×ox
Δ×o×Δ×○×Δ×0 Data Figure 3 Figure 7 Figure 80 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15

Claims (1)

[Claims] A sample data string with a sample frequency f1 (Hz) is converted to a sample data string with a sample frequency of n×f1 (Hz) using a linear interpolation filter, and any other sample frequency f2 (Hz) (f2< For each sample point of f1), select the temporally closest sample data among the sample points of n×f1 (Hz), and set the sampling frequency f2.
A digital data conversion method characterized by converting into a sample data string.