JPS6369295A - Wiring board - Google Patents

Wiring board

Info

Publication number
JPS6369295A
JPS6369295A JP61213448A JP21344886A JPS6369295A JP S6369295 A JPS6369295 A JP S6369295A JP 61213448 A JP61213448 A JP 61213448A JP 21344886 A JP21344886 A JP 21344886A JP S6369295 A JPS6369295 A JP S6369295A
Authority
JP
Japan
Prior art keywords
wiring board
resistor
circuit
conductors
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61213448A
Other languages
Japanese (ja)
Inventor
和彦 野沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP61213448A priority Critical patent/JPS6369295A/en
Publication of JPS6369295A publication Critical patent/JPS6369295A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔概 要〕 配線基板であって、回路部品を実装できる絶縁基板内で
、複数の導体が互いに絶縁され且つ多層に形成されてお
り、そのうち少なくとも2つの導体の間に電気回路とし
て必要な回路素子を一体的に形成することにより、基板
での実装密度を上げることができ且つ電気回路の高速動
作が可能となる。
[Detailed Description of the Invention] [Summary] A wiring board, in which a plurality of conductors are insulated from each other and formed in multiple layers within an insulating board on which circuit components can be mounted, and there is a conductor between at least two of the conductors. By integrally forming the circuit elements necessary for the electric circuit, it is possible to increase the packaging density on the board and to enable high-speed operation of the electric circuit.

〔産業上の利用分野〕[Industrial application field]

本発明は配線基板に関し、例えば、IC等の電子回路部
品を実装し、該電子回路部品を高周波で動作させる場合
に適した配線基板に関するものである。
The present invention relates to a wiring board, and for example, to a wiring board suitable for mounting electronic circuit components such as ICs and operating the electronic circuit components at high frequencies.

〔従来の技術〕[Conventional technology]

従来から、各種の電子装置に用いられている配線基板上
には、常に一定の目的のため所定位置に接続すべき抵抗
器、コンデンサ等の電子回路部品が実装されている。
2. Description of the Related Art Conventionally, electronic circuit components such as resistors and capacitors, which should always be connected to predetermined positions for a certain purpose, are mounted on wiring boards used in various electronic devices.

例えば、回路基板に実装された電子回路部品によって形
成される電気回路が、超高速パルスに応動するようにし
たものであれば、高周波で動作可能とすべき電子回路部
品が該回路基板上で必要となる。かような回路部品とし
ては、超高速パルス等による高周波信号を効率よく伝送
するために必要なインピーダンス整合用の終端抵抗器、
電源系からの雑音を排除して回路の安定な動作を実現す
るためのバイパスコンデンサ等が挙げられる。
For example, if an electrical circuit formed by electronic circuit components mounted on a circuit board is designed to respond to ultra-high-speed pulses, electronic circuit components that can operate at high frequencies are required on the circuit board. becomes. Such circuit components include terminating resistors for impedance matching, which are necessary for efficiently transmitting high-frequency signals such as ultra-high-speed pulses;
Examples include bypass capacitors that eliminate noise from the power supply system and ensure stable operation of the circuit.

第3図に、従来から一般的に用いられている多層の配線
基板を示す。この配線基板を断面でみれば、一体的に板
状となっている絶縁体11の表面および裏面に接地導体
13および接地導体14が形成されている。また、2つ
の接地導体13.14の間で且つ絶縁体11中において
、複数の電源線15と、ある層の信号線17と、別な層
で複数の信号線19とが互いに絶縁されて配置されてい
る。このように、多数の導体で成る接地導体13および
14.電源線15.信号線17および信号線19が、絶
縁体11に対して多層となるように形成されている。
FIG. 3 shows a conventionally commonly used multilayer wiring board. When this wiring board is viewed in cross section, a ground conductor 13 and a ground conductor 14 are formed on the front and back surfaces of an insulator 11 that is integrally formed into a plate. Furthermore, between the two ground conductors 13 and 14 and in the insulator 11, a plurality of power supply lines 15, a signal line 17 in one layer, and a plurality of signal lines 19 in another layer are arranged so as to be insulated from each other. has been done. In this way, the ground conductors 13 and 14 . Power line 15. The signal line 17 and the signal line 19 are formed in multiple layers relative to the insulator 11 .

このような配線基板に、上述した終端抵抗器。The above-mentioned terminating resistor is attached to such a wiring board.

バイパスコンデンサ等の回路部品の実装方法としては、
以下に述べる方法が提案されていた。それら各種の方法
を基本とした従来の基板および回路部品の実装概念を、
図を用いて説明する。
The method for mounting circuit components such as bypass capacitors is as follows:
The method described below was proposed. The conventional board and circuit component mounting concepts based on these various methods are
This will be explained using figures.

(イ)個別部品を基板表面に実装する方法。(a) A method of mounting individual components on the surface of a board.

第4図は、抵抗器、コンデンサ等の個別部品を基板表面
に実装する方法を示す。ここで、配線基板を形成する絶
縁体21中において、導体である電源線23および信号
線25が形成されている。
FIG. 4 shows a method for mounting individual components such as resistors and capacitors on the surface of the substrate. Here, a power supply line 23 and a signal line 25, which are conductors, are formed in an insulator 21 forming a wiring board.

また、この配線基板の両面には接地導体27,28が形
成されており、その表面にはIC29が搭載されている
。IC29の電源入力端子31は電源線23に接続され
、また、IC29の信号端子33は信号線25に接続さ
れて、当該IC29の動作に必要な電源が供給されると
共に、動作上の信号の入出力が行なわれるようになって
いる。
Further, ground conductors 27 and 28 are formed on both sides of this wiring board, and an IC 29 is mounted on the surface thereof. The power input terminal 31 of the IC 29 is connected to the power line 23, and the signal terminal 33 of the IC 29 is connected to the signal line 25, so that the power necessary for the operation of the IC 29 is supplied, and the input of operational signals is provided. Output is now being generated.

表面の接地導体27中に、所定大の導体剥離部35を形
成し、それを介して電源入力端子31を挿入すると共に
、該電源入力端子31と接地導体27との間にバイパス
コンデンサ37が装着されている。また、同様にして、
接地導体27中に形成した所定大の他の導体剥離部36
を介して信号端子33を挿入すると共に、該信号端子3
3と接地導体27との間に終端抵抗器39が装着されて
いる。
A conductor peeling part 35 of a predetermined size is formed in the ground conductor 27 on the surface, and the power input terminal 31 is inserted through it, and a bypass capacitor 37 is installed between the power input terminal 31 and the ground conductor 27. has been done. Also, in the same way,
Another conductor peeling portion 36 of a predetermined size formed in the ground conductor 27
The signal terminal 33 is inserted through the signal terminal 3.
A terminating resistor 39 is installed between 3 and the ground conductor 27.

(ロ)基板の貫通孔内に回路素子を収納する方法。(b) A method of storing circuit elements in through-holes of a board.

第5図は、配線基板の上下配線層間を接続する貫通孔(
スルーホール形成用の孔に相当する)内に、回路素子を
挿入して収納する方法を示す。ここで、配線基板を形成
する絶!!基板41の両面には、所望の配線パターン4
3が導体によって形成されている。両面に設けた導体の
間を結ぶ形で、絶縁基板41中に形成された貫通孔45
1貫通孔47に、終端抵抗器およびバイパスコンデンサ
として、チップ状の抵抗器49.コンデンサ51が挿入
される。
Figure 5 shows through holes (
A method of inserting and storing a circuit element into a hole (corresponding to a hole for forming a through hole) is shown. Now, let's talk about how to form a wiring board! ! A desired wiring pattern 4 is formed on both sides of the board 41.
3 is formed of a conductor. A through hole 45 is formed in the insulating substrate 41 to connect the conductors provided on both sides.
A chip-shaped resistor 49.1 is inserted into the through hole 47 as a terminating resistor and a bypass capacitor. A capacitor 51 is inserted.

(ハ)配線基板に配置するIC内に、回路部品を内蔵す
る方法。
(c) A method of incorporating circuit components into an IC placed on a wiring board.

第6図は、これらの終端抵抗器、バイパスコンデンサ等
の回路部品を、配線基板に搭載するIC内に内蔵する方
法を示す。この方法にあっても、第4図と同様に形成さ
れる配線基板上に、IC60が実装される。このIC6
0では、そのICケース61によってICチップ63が
封入されている。このICチップ63内において、バイ
パスコンデンサに相当するチップ内蔵コンデンサ65お
よび終端抵抗器に相当するチップ内蔵抵抗体67を、そ
の素子(ICチップ63)中に付加的に形成している。
FIG. 6 shows a method of incorporating circuit components such as a terminating resistor and a bypass capacitor into an IC mounted on a wiring board. Even in this method, the IC 60 is mounted on a wiring board formed in the same manner as shown in FIG. This IC6
0, an IC chip 63 is enclosed by the IC case 61. In this IC chip 63, a built-in chip capacitor 65 corresponding to a bypass capacitor and a built-in chip resistor 67 corresponding to a terminating resistor are additionally formed in the element (IC chip 63).

以上のような手段によって、超高速パルスに応動するよ
うに、高周波信号を効率よく伝送するために必要なイン
ピーダンス整合用の終端抵抗器。
A terminating resistor for impedance matching is necessary for efficiently transmitting high-frequency signals in response to ultra-high-speed pulses using the above-mentioned means.

および電源系からの雑音を排除して回路の安定な動作を
実現するためのバイパスコンデンサを実装するようにし
ている。
A bypass capacitor is also installed to eliminate noise from the power supply system and ensure stable operation of the circuit.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、上述した従来方式にあっては、各種の問題点
があった。
By the way, the conventional method described above has various problems.

先ず、第4図に示すような配線基板上に、終端抵抗器お
よびバイパスコンデンサを実装する方法にあっては、配
線基板の製作が簡単であるが、回路部品の実装状態を高
密度にできない。例えば、IC29による回路動作が高
速となることに応じて、必然的に回路部品の実装状態を
高密度としなければならない。特に、ICの封入パッケ
ージを用いることなく、ICチップ状態で配線基板に実
装することが必要となる場合、バイパスコンデンサ37
および終端抵抗器39が配線基板上で占める総面積は、
ICチップが占める面積より大きなものとなる。そのた
め、チップ状態でICを実装することによる実装密度の
改善効果を図ることはできないという問題点があった。
First, in the method of mounting a terminating resistor and a bypass capacitor on a wiring board as shown in FIG. 4, the wiring board can be easily manufactured, but the circuit components cannot be mounted at a high density. For example, as the circuit operation by the IC 29 becomes faster, circuit components must necessarily be mounted at a higher density. In particular, when it is necessary to mount the IC chip on a wiring board without using an encapsulated package, the bypass capacitor 37
And the total area occupied by the termination resistor 39 on the wiring board is:
The area is larger than that occupied by an IC chip. Therefore, there is a problem in that it is not possible to improve the packaging density by mounting the IC in the form of a chip.

また、第5図に示した方法にあっても、個別部品たる抵
抗器49.コンデンサ51を絶縁基板41の貫通孔45
.47に挿入するものである。貫通孔45.47の大き
さに起因して、これらの個別部品の小型化には限界があ
り、当該貫通孔を大きくしなければならない。従って、
個別部品の表面実装の場合と同様に、高実装密度化が図
れないという問題点があった。また、抵抗器49.コン
デンサ51を配vA基板に実装する際には、それらの個
別部品を半田付けあるいは導電性ペースト等で接続する
必要があり、それらの接続手段における信頼性も高くは
ないという欠点があった。
Further, even in the method shown in FIG. 5, the resistor 49, which is an individual component. The capacitor 51 is inserted into the through hole 45 of the insulating substrate 41.
.. 47. Due to the size of the through-holes 45, 47, there is a limit to the miniaturization of these individual parts, and the through-holes have to be enlarged. Therefore,
As with surface mounting of individual components, there is a problem in that high mounting density cannot be achieved. Also, resistor 49. When mounting the capacitor 51 on the vA board, it is necessary to connect these individual components by soldering or conductive paste, and there is a drawback that the reliability of these connection means is not high.

更に、第6図の方法では、IC60のICケース61内
にチップ内蔵コンデンサ65およびチップ内蔵抵抗体6
7を含ませており、IC60を実装する際、別個な終端
抵抗器およびバイパスコンデンサを設ける必要はないの
で、実装密度を高めるための制限とはならない。しがし
ながら、第7図に示すように、複数のICを接続する場
合において、第11C71(例えば送信側)と他の第2
1C73とを、特性インピーダンスZ0の配線部分75
で接続する場合、当該配線部分75の終端側でチップ内
蔵抵抗体67を設けていた。このチップ内蔵抵抗体67
の抵抗値R7は、配線部分75の特性インピーダンスZ
0と同じである。これに対して、第7図(B)に示すよ
うに、配線部分75を介して第1TC71に接続される
ICが、第21C73および第31C77というように
分岐した構成となる場合、別な配線部分751にょって
第2IC73と第31C77とを接続して、別な配線部
分751側においてのみチップ内蔵抵抗体67を形成す
ればよい。つまり、第2IC730入力側には、チップ
内蔵抵抗体67を設ける必要はない。
Furthermore, in the method shown in FIG.
7, and there is no need to provide a separate termination resistor and bypass capacitor when mounting the IC 60, so there is no restriction on increasing the packaging density. However, as shown in FIG. 7, when connecting multiple ICs, the
1C73 and the wiring portion 75 with characteristic impedance Z0.
In this case, a built-in chip resistor 67 is provided at the terminal end of the wiring portion 75. This chip built-in resistor 67
The resistance value R7 is the characteristic impedance Z of the wiring portion 75.
Same as 0. On the other hand, as shown in FIG. 7(B), when the IC connected to the first TC 71 via the wiring portion 75 has a branched configuration such as the 21C 73 and the 31C 77, another wiring portion It is only necessary to connect the second IC 73 and the 31st IC 77 by means of the second IC 751 and form the built-in chip resistor 67 only on the other wiring portion 751 side. That is, there is no need to provide the chip built-in resistor 67 on the input side of the second IC 730.

従って、第7図(A)に示すように1対1のIC接続と
異なり、同図(B)に示すように、1つのrc比出力ら
分岐接続する場合には、その終端方法を変える必要があ
る。そのため、ICとしてのの汎用性を損なう欠点があ
った。このように、回路素子を内蔵させることは、IC
の歩留まりを低下させてしまうという問題点があった。
Therefore, unlike the one-to-one IC connection as shown in Figure 7 (A), when branching from one RC ratio output as shown in Figure 7 (B), it is necessary to change the termination method. There is. Therefore, there was a drawback that the versatility as an IC was impaired. In this way, incorporating circuit elements means that the IC
There was a problem in that the yield of

本発明は、このような点にかんがみて創作されたもので
あり、例えば超高速パルスに応動するように回路基板に
設けられた電気回路において、インピーダンス整合用終
端抵抗器、バイパスコンデンサ等の回路素子の配線基板
への実装密度の向上を図り、回路の動作用に装着される
rc等の回路部品の汎用性を損なうことのないようにし
た配線基板を提供することを目的としている。
The present invention was created in view of these points, and is applicable to circuit elements such as impedance matching terminating resistors and bypass capacitors in electrical circuits provided on circuit boards that respond to ultra-high-speed pulses. It is an object of the present invention to provide a wiring board which improves the packaging density of the wiring board and which does not impair the versatility of circuit components such as RCs mounted for circuit operation.

〔問題点を解決するための手段〕[Means for solving problems]

このような目的を達成するために、本発明による配線基
板は、表面に回路部品を実装できる絶縁基板と、該絶縁
基板の内部で互いに絶縁され且つ多層に形成されて前記
回路部品に接続され得るように設けられた複数の導体と
、該複数の導体のうち少なくとも2つの導体の間で絶縁
体中を貫通する形で形成された回路素子とを含むように
一体的に構成されている。
In order to achieve such an object, the wiring board according to the present invention includes an insulating substrate on which circuit components can be mounted, and a multilayer structure that is insulated from each other and connected to the circuit components inside the insulating substrate. It is integrally constructed to include a plurality of conductors provided in this manner, and a circuit element formed to penetrate through an insulator between at least two of the plurality of conductors.

〔作 用〕[For production]

回路部品が実装できる絶縁基板内で、互いに絶縁し且つ
多層に複数の導体を形成し、該2つの導体の間に回路素
子を一体的に形成している。
A plurality of conductors are formed in multiple layers and insulated from each other within an insulating substrate on which circuit components can be mounted, and a circuit element is integrally formed between the two conductors.

絶縁基板上に実装される回路部品による電気回路は、こ
の回路素子が接続された形となり、高速動作が可能とな
る。
An electric circuit made up of circuit components mounted on an insulating substrate has a form in which these circuit elements are connected, and high-speed operation is possible.

本発明にあっては、本来回路部品が実装できる絶縁基板
内に、回路素子を形成していることにより実装密度が高
くなる。
In the present invention, packaging density is increased by forming circuit elements within an insulating substrate on which circuit components can originally be mounted.

〔実施例〕〔Example〕

以下、図面に基づいて本発明の実施例について詳細に説
明する。
Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

±−尖拒班免1衣 第1図は、本発明の一実施例における配線基板の構成を
示す。ここで、第1図(A)は本発明実施例においてバ
イパスコンデンサ97および終端抵抗器99を形成して
接続した全体構成を示す。
Figure 1 shows the configuration of a wiring board in an embodiment of the present invention. Here, FIG. 1(A) shows the overall configuration in which a bypass capacitor 97 and a termination resistor 99 are formed and connected in an embodiment of the present invention.

また、同図(B)は、図(A>における終端抵抗器99
の周辺を拡大して示す。同図(C)は、図(A)におけ
るバイパスコンデンサ97の周辺を拡大して示す。
In addition, the same figure (B) shows the termination resistor 99 in the figure (A>
The area around the area is shown enlarged. FIG. 5C shows an enlarged view of the vicinity of the bypass capacitor 97 in FIG.

図において、配線基板を形成する絶縁体81中において
、電源線83および信号線85が形成されている。また
、絶縁体81の表面に接地導体87が、裏面に接地導体
88がそれぞれ形成されており、該接地導体87側にI
C89が装着されている。IC89の電源入力端子91
は、接地導体87での所定大の剥離領域92を貫通して
電源線83に接続されている。IC89の信号端子93
も、接地導体87での別な所定大の剥離領域94を貫通
して信号線85に接続されている。これにより、IC8
9の動作に必要な電源が供給されると共に、動作上の信
号の入出力が行なわれるようになっている。また、別な
電源線95が絶縁体81中に形成されている。
In the figure, a power line 83 and a signal line 85 are formed in an insulator 81 forming a wiring board. Further, a grounding conductor 87 is formed on the front surface of the insulator 81, and a grounding conductor 88 is formed on the back surface, and an I
C89 is installed. Power input terminal 91 of IC89
is connected to the power supply line 83 by passing through a peeled area 92 of a predetermined size in the ground conductor 87 . IC89 signal terminal 93
The ground conductor 87 is also connected to the signal line 85 by passing through another separated area 94 of a predetermined size. As a result, IC8
The power supply necessary for the operation of 9 is supplied, and operational signals are input and output. Further, another power supply line 95 is formed in the insulator 81.

電源入力端子91は、電源線830反対側に更に伸長し
ており、バイパスコンデン・す97を介して接地導体8
8に接続されている。また、信号端子93は、信号線8
50反対側に更に伸長しており、終端抵抗器99を介し
て電源線95に接続されている。
The power input terminal 91 further extends to the opposite side of the power line 830 and is connected to the ground conductor 8 via a bypass capacitor 97.
8 is connected. Further, the signal terminal 93 is connected to the signal line 8
It further extends to the opposite side of 50 and is connected to the power supply line 95 via a terminating resistor 99 .

なお、このIC89は封入用パッケージを用いないチッ
プのみによるICである。
Note that this IC 89 is an IC consisting only of chips without using an encapsulating package.

第2図は、第1図に示すように形成される配線基板にお
いて、複数のICを装着する基板に、超高速ハルスに応
動できるように、インピーダンス整合用終端抵抗器およ
びバイパスコンデンサを一体的に形成した場合を示す。
Figure 2 shows that in the wiring board formed as shown in Figure 1, a termination resistor for impedance matching and a bypass capacitor are integrally installed on the board on which multiple ICs are mounted so that it can respond to ultra-high speed Hals. The case where it is formed is shown.

第2図において、チップ状態での4つのIC891〜I
C894が、配線基板に対して直接に搭載されるように
なっている。このうち、IC891の信号入力端子93
■1をIC894の信号出力端子9304と、IC89
3の信号出力端子9303をIC891の信号入力端子
9311□およびIC892の信号入力端子93I2と
、それぞれ特性インピーダンスがZである信号線で接続
する。この間で、超高速パルス伝送を行なうものとする
In FIG. 2, four ICs 891 to I in chip form are shown.
C894 is mounted directly on the wiring board. Among these, the signal input terminal 93 of IC891
■1 to the signal output terminal 9304 of IC894 and IC89
The signal output terminal 9303 of No. 3 is connected to the signal input terminal 9311□ of the IC 891 and the signal input terminal 93I2 of the IC 892 through signal lines each having a characteristic impedance of Z. During this time, it is assumed that ultrahigh-speed pulse transmission is performed.

それぞれの入力端子直前で、インピーダンス整合用の終
端抵抗器991 (抵抗値R1)および終端抵抗器99
2(抵抗値R2)を、信号線と電源線843との間に接
続している。この電源線843は、電源■3を供給する
ためのものである。更に、各ICに2種類の電源Vl、
V2を供給するものとし、それに必要な電源線841お
よび電源線842を形成している。
Immediately before each input terminal, a terminating resistor 991 (resistance value R1) and a terminating resistor 99 for impedance matching are installed.
2 (resistance value R2) is connected between the signal line and the power supply line 843. This power line 843 is for supplying power (3). Furthermore, each IC has two types of power supply Vl,
V2 is supplied, and necessary power supply lines 841 and 842 are formed.

各ICの電源入力端子と基板の接地導体との間に、容W
t値01〜C8のバイパスコンデンサ971〜978を
接続する。これらのコンデンサおよび終端抵抗器は、基
板の断面方向であり、基板の平面と垂直な方向にて眉間
にわたって柱状に形成する。
There is a capacitance W between the power input terminal of each IC and the ground conductor of the board.
Bypass capacitors 971 to 978 with t values 01 to C8 are connected. These capacitors and terminating resistors are formed in a columnar shape extending between the eyebrows in a direction perpendicular to the plane of the substrate, which is the cross-sectional direction of the substrate.

このように、配線基板の絶縁体81中に形成することに
より、結果的にIC89の高速動作に必要なバイパスコ
ンデンサ97および終端抵抗器99が個別的に実装され
たことになる。
By forming them in the insulator 81 of the wiring board in this manner, the bypass capacitor 97 and the termination resistor 99 necessary for high-speed operation of the IC 89 are individually mounted.

ところで、そのように実装される終端抵抗器99の一体
形成を実現するには、液相における高抵抗金属のメッキ
技術により柱状構造を形成する方法、金属表面にCVD
等の気相成長で高抵抗材料を選択的に柱状成長させる方
法、抵抗形成部分にペースト状の高抵抗材料を流し込み
固化させた後に金属で封止する方法等、各種の抵抗形成
技法がある。その場合の抵抗値の制御は、抵抗材料の厚
さで任意に行なうことができる。
By the way, in order to realize integral formation of the termination resistor 99 mounted in this way, there are two methods: forming a columnar structure by plating a high-resistance metal in a liquid phase, and applying CVD to a metal surface.
There are various resistor forming techniques, such as a method of selectively growing a high-resistance material in a columnar shape using vapor phase growth, and a method of pouring a paste-like high-resistance material into a resistor-forming area, solidifying it, and then sealing it with metal. In this case, the resistance value can be controlled arbitrarily by adjusting the thickness of the resistive material.

ここでは、終端抵抗器99の実装法として、微細な柱状
抵抗形成法について説明する。
Here, as a method for mounting the termination resistor 99, a method for forming a fine columnar resistor will be described.

例えば、PdAu、PdAg等の金属混晶1合金を、電
子ビーム蒸着法によりマスクを介して、絶縁体81のあ
る層において蒸着する。これによリ、必要な個所に終端
抵抗器99が形成される。
For example, a metal mixed crystal 1 alloy such as PdAu or PdAg is deposited on a certain layer of the insulator 81 through a mask by electron beam evaporation. Thereby, the termination resistor 99 is formed at the required location.

しかる後、その層を絶縁体81となる樹脂で膜形成する
。次に、この形成された終端抵抗器99と接続すべき信
号線その他の線導体を、樹脂膜上に形成する。従って、
所望の線導体間にて、終端抵抗器99が実装されたこと
になる。なお、この場合での終端抵抗器99の抵抗値は
、抵抗材料となるPdAu、PdAg等の金属の組成比
を変えることによって制御できる。
Thereafter, that layer is formed with a resin that will become the insulator 81. Next, signal lines and other line conductors to be connected to the formed termination resistor 99 are formed on the resin film. Therefore,
This means that the terminating resistor 99 is mounted between the desired line conductors. Note that the resistance value of the terminating resistor 99 in this case can be controlled by changing the composition ratio of metals such as PdAu and PdAg serving as resistance materials.

また、絶縁体81内で配線層間を連結するように予め設
けた柱状の孔に、スクリーン印刷等の技法を用い、ペー
スト状の抵抗材料を流し込んだ後に焼結する。そのペー
スト状の抵抗材料は、RuO□系のペースト(セラミッ
ク等の高温に耐え得るもの)、微粒子抵抗と高分子粒子
との高分子厚膜ペーストがある。これらの材料は、高温
で焼結される。
Furthermore, using a technique such as screen printing, a paste-like resistance material is poured into columnar holes previously provided in the insulator 81 to connect wiring layers, and then sintered. Paste-like resistance materials include RuO□-based paste (such as ceramic, which can withstand high temperatures) and polymer thick film paste of fine particle resistance and polymer particles. These materials are sintered at high temperatures.

例えば、終端抵抗器99において、所望の抵抗値R(5
0Ω)を実現する場合を考える。いま、終端抵抗器99
が断面円形の柱状形状とし、その直径および長さが共に
100μmとする。使用する抵抗材料の特性として、例
えば15μmの厚さでのシート抵抗値R0とすると、そ
の体積抵抗率ρは15 X 1 o−”Roである。す
ると、その体積抵抗率ρおよび終端抵抗器99のサイズ
に基づいて、抵抗値Rは、R”Ro xQ、2として与
えられる。従って、例えばRO=250Ω/口の材料で
あれば、R=50Ωを得ることができる。
For example, in the termination resistor 99, a desired resistance value R (5
Consider the case of realizing 0Ω). Now, the terminating resistor 99
It has a columnar shape with a circular cross section, and its diameter and length are both 100 μm. As a characteristic of the resistive material used, for example, if the sheet resistance value R0 is 15 μm thick, its volume resistivity ρ is 15×1 o−”Ro.Then, the volume resistivity ρ and the terminating resistor 99 Based on the size of , the resistance value R is given as R''Ro xQ,2. Therefore, for example, if the material has RO=250Ω/mouth, R=50Ω can be obtained.

また、上述したように実装されるバイパスコンデンサ9
7を実現することも、終端抵抗器99と同様にすればよ
いので容易である。つまり、先の抵抗材料に代えて誘電
体を用いればよく、これらの形成技法は現状の多層基板
形成技術の延長線上にあるため、当業者であれば容易に
実現できるものである。
Also, the bypass capacitor 9 mounted as described above
7 is also easy to implement because it can be done in the same way as the terminating resistor 99. In other words, a dielectric material may be used in place of the above-mentioned resistive material, and since these formation techniques are an extension of the current multilayer substrate formation technology, those skilled in the art can easily realize this.

■、 方 のまとめ このようにして、絶縁体81の中で配線層間に柱状の終
端抵抗器99およびバイパスコンデンサ97を形成して
、当該配線基板に装着されるrc89の動作上にて必要
な回路形成となる。その場合、配線基板の表面上に実装
されず、また、I’C89の内部にも形成されていない
■Summary of the method In this way, a columnar termination resistor 99 and a bypass capacitor 97 are formed between the wiring layers in the insulator 81, and the circuits necessary for the operation of the rc89 mounted on the wiring board are formed. It becomes a formation. In that case, it is not mounted on the surface of the wiring board, nor is it formed inside the I'C 89.

従って、高速パルス伝送に不可欠な終端抵抗器99およ
びバイパスコンデンサ97を配線基板内に埋め込んだ構
造として、回路素子の実装に伴う配線を短縮している。
Therefore, the termination resistor 99 and bypass capacitor 97, which are essential for high-speed pulse transmission, are embedded in the wiring board to shorten the wiring required for mounting the circuit elements.

これにより1、電気回路の高速動作を制限する主たる要
因である減衰、伝搬遅延を大幅に低減でき、回路動作の
高速化が図れることとなる。
As a result, 1. Attenuation and propagation delay, which are the main factors that limit high-speed operation of electric circuits, can be significantly reduced, and the speed of circuit operation can be increased.

ここで、本発明実施例を従来例と比較すれば、次のよう
な利点がある。先ず、抵抗、コンデンサを基板表面に実
装する場合と比較して、それら個別な部品が占有してい
た部分を他に有効的に利用できることに因り、超高密度
実装が可能となる。
Here, if the embodiment of the present invention is compared with the conventional example, it has the following advantages. First, compared to the case where resistors and capacitors are mounted on the surface of a substrate, the areas occupied by these individual components can be effectively used for other purposes, making ultra-high-density mounting possible.

また、IC内に終端抵抗器99を内蔵させず、且つ、終
端抵抗器99の抵抗値を任意に設定可能であるので、I
Cへの該終端抵抗器99の接続の有無にかかわらず、当
該ICの汎用性が損なわれるということはない。
Furthermore, since the terminating resistor 99 is not built into the IC and the resistance value of the terminating resistor 99 can be set arbitrarily, the I
Regardless of whether or not the termination resistor 99 is connected to C, the versatility of the IC is not impaired.

■、→lの、・形IlE様 なお、上述した本発明実施例にあっては、抵抗器および
コンデンサの形状を断面円形状の柱状としたが、これに
限られることなく、他の断面形状を有する柱状のもので
もよい。
■、→l、・Shape ILE In the above-described embodiments of the present invention, the shapes of the resistors and capacitors are columnar with a circular cross section. It may also be a columnar one having the following.

また、上述した本発明実施例による配線基板上に搭載さ
れる電子回路部品として、ICを示したが、その他の回
路部品であってもよい。
Moreover, although an IC is shown as an electronic circuit component mounted on the wiring board according to the embodiment of the present invention described above, other circuit components may be used.

更に、本発明はその他にも各種の変形態様があることは
当業者であれば容易に推考できるであろう。
Furthermore, those skilled in the art will easily guess that the present invention has various other modifications.

〔発明の効果〕〔Effect of the invention〕

上述したように、本発明によれば、回路部品を搭載でき
る絶縁基板内で互いに絶縁され且つ多層に形成された導
体の間に、高周波動作に必要なインピーダンス整合用終
端抵抗器、バイパスコンデンサ等の回路部品を実装する
ことにより、基板上での実装密度の向上が図られると共
に、当該回路の動作用に装着されるIC等の汎用性を損
なうことがないので、実用的には極めて有用である。
As described above, according to the present invention, impedance matching terminating resistors, bypass capacitors, etc. necessary for high frequency operation are installed between conductors that are insulated from each other and formed in multiple layers within an insulating substrate on which circuit components can be mounted. By mounting circuit components, the mounting density on the board can be improved, and the versatility of ICs etc. installed for the operation of the circuit is not impaired, so it is extremely useful in practical terms. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による配線基板の構成を示す
概略断面図、 第2図は本発明の一実施例による配線基板に複数のIC
を実装した状態を示す側面図、 第3図は一般的な配線基板を示す断面図、第4図は個別
部品を基板表面に実装する従来例の説明図、 第5図は基板の貫通孔内に回路素子を収納する従来例の
説明図、 第6図は配線基板に配置するIC内に回路部品を内蔵す
る従来例の説明図、 第7図は配線基板に搭載されるICが1対1で接続され
る場合および1対2に分岐される場合の説明図である。 図において、 11.21.81は絶縁体、 13.27,87.88は接地導体、 15.23.83,84.95は電源線、17.19.
25.85は信号線、 29.89.891〜894はIC。 31.91は電源入力端子、 33.93は信号端子、 37.97,971〜978はバイパスコンデンサ、 39.99,991.992は終端抵抗器、41は絶縁
基板、 43は配線パターン、 45.47は貫通孔、 49は抵抗器、 51はコンデンサ、 63はICチップ、 65はチップ内蔵コンデンサ、 67はチップ内蔵抵抗体である。 (A) 実施例の説明図 第1図 第4図
FIG. 1 is a schematic sectional view showing the configuration of a wiring board according to an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view showing the configuration of a wiring board according to an embodiment of the present invention.
Fig. 3 is a cross-sectional view showing a general wiring board, Fig. 4 is an explanatory diagram of a conventional example in which individual components are mounted on the board surface, and Fig. 5 is a diagram showing the inside of a through-hole in the board. Figure 6 is an explanatory diagram of a conventional example in which circuit elements are housed in an IC mounted on a wiring board. Figure 7 is an explanatory diagram of a conventional example in which circuit elements are housed in an IC mounted on a wiring board. FIG. 4 is an explanatory diagram of a case in which a connection is made in a 1-to-2 manner and a case in which a connection is made in a 1:2 manner. In the figure, 11.21.81 is an insulator, 13.27, 87.88 are ground conductors, 15.23.83, 84.95 are power lines, 17.19.
25.85 is a signal line, 29.89.891-894 are ICs. 31.91 is a power input terminal, 33.93 is a signal terminal, 37.97, 971 to 978 are bypass capacitors, 39.99, 991.992 is a termination resistor, 41 is an insulating substrate, 43 is a wiring pattern, 45. 47 is a through hole, 49 is a resistor, 51 is a capacitor, 63 is an IC chip, 65 is a chip built-in capacitor, and 67 is a chip built-in resistor. (A) Explanatory diagram of the example Fig. 1 Fig. 4

Claims (3)

【特許請求の範囲】[Claims] (1)表面に回路部品を実装できる絶縁基板と、該絶縁
基板の内部で互いに絶縁され且つ多層に形成されて前記
回路部品に接続され得るように設けられた複数の導体と
、該複数の導体のうち少なくとも2つの導体の間で絶縁
体中を貫通する形で形成された回路素子とを含むように
一体的に構成したことを特徴とする配線基板。
(1) An insulating substrate on which a circuit component can be mounted; a plurality of conductors that are insulated from each other and formed in multiple layers inside the insulating substrate so that they can be connected to the circuit component; and the plurality of conductors. 1. A wiring board integrally configured to include a circuit element formed to penetrate through an insulator between at least two of the conductors.
(2)前記回路素子は、柱状の抵抗素子であることを特
徴とする特許請求の範囲第1項記載の配線基板。
(2) The wiring board according to claim 1, wherein the circuit element is a columnar resistance element.
(3)前記回路素子は、柱状のコンデンサであることを
特徴とする特許請求の範囲第1項記載の配線基板。
(3) The wiring board according to claim 1, wherein the circuit element is a columnar capacitor.
JP61213448A 1986-09-10 1986-09-10 Wiring board Pending JPS6369295A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61213448A JPS6369295A (en) 1986-09-10 1986-09-10 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61213448A JPS6369295A (en) 1986-09-10 1986-09-10 Wiring board

Publications (1)

Publication Number Publication Date
JPS6369295A true JPS6369295A (en) 1988-03-29

Family

ID=16639391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61213448A Pending JPS6369295A (en) 1986-09-10 1986-09-10 Wiring board

Country Status (1)

Country Link
JP (1) JPS6369295A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03106053A (en) * 1989-09-15 1991-05-02 Internatl Business Mach Corp <Ibm> Design system for vlsi chip placed on carrier, and module designed by this
WO1996009645A1 (en) * 1994-09-20 1996-03-28 Hitachi, Ltd. Semiconductor device and its mounting structure
JPH09139573A (en) * 1995-09-14 1997-05-27 Nec Corp Multilayer printed board
JP2003023271A (en) * 2001-03-21 2003-01-24 Siemens Ag Electronic device
US6678169B2 (en) 2000-05-31 2004-01-13 Kabushiki Kaisha Toshiba Printed circuit board and electronic equipment using the board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03106053A (en) * 1989-09-15 1991-05-02 Internatl Business Mach Corp <Ibm> Design system for vlsi chip placed on carrier, and module designed by this
WO1996009645A1 (en) * 1994-09-20 1996-03-28 Hitachi, Ltd. Semiconductor device and its mounting structure
JPH09139573A (en) * 1995-09-14 1997-05-27 Nec Corp Multilayer printed board
US6678169B2 (en) 2000-05-31 2004-01-13 Kabushiki Kaisha Toshiba Printed circuit board and electronic equipment using the board
JP2003023271A (en) * 2001-03-21 2003-01-24 Siemens Ag Electronic device

Similar Documents

Publication Publication Date Title
US5635761A (en) Internal resistor termination in multi-chip module environments
US4210885A (en) Thin film lossy line for preventing reflections in microcircuit chip package interconnections
US6194979B1 (en) Ball grid array R-C network with high density
EP0980079B1 (en) Low cross-talk ball grid array resistor network
US20130239408A1 (en) Power and ground vias for power distribution systems
US4860166A (en) Integrated circuit termination device
JPS6369295A (en) Wiring board
KR100560571B1 (en) Interconnect
GB2248346A (en) Multilayer semiconductor circuit module
US5736784A (en) Variable-width lead interconnection structure and method
US5504986A (en) Method of manufacturing collinear terminated transmission line structure with thick film circuitry
US5990421A (en) Built in board resistors
US5763060A (en) Printed wiring board
US6239400B1 (en) Method and device for connecting two millimeter elements
US7626828B1 (en) Providing a resistive element between reference plane layers in a circuit board
JP2703456B2 (en) Wiring board
JP3940537B2 (en) Multilayer wiring board
JPS6342437B2 (en)
JPH0639583A (en) Solder paste and circuit board
JP3752409B2 (en) Multilayer wiring board
JP3954415B2 (en) Auxiliary package for wiring
JPH0239604A (en) Delay circuit structure
JPH03155202A (en) Printed circuit board
JPH01264249A (en) Pin for board, board equipped with pin and printed-circuit board
JPS6249691A (en) High frequency connection wire inside printed wiring board