JPS6368930A - Microprocessor - Google Patents

Abstract

PURPOSE:To store a large microprogram by providing one hip with a ROM for storing part of the program and a RAM for storing the rest, and also providing an external control storage which backs up the rest. CONSTITUTION:A microprocessor 1 is provided with the control storage ROM 10, a control storage cache 20 consisting of the control storage RAM 11 and a cache control part 12, a mu-instruction register 13, a mu-sequencer 14, a mu-instruction decoder 15, and an instruction processing unit 16. Further, the external control storage 2 is provided outside the chip 1 and connected to the control storage cache 20 by using a mu-address bus 31 and a data bus 32. Thus, basic instructions are stored in the ROM 10 and decimal arithmetic instruction, floating-point arithmetic instructions, system control, RAS, etc., are stored in the RAM 11; and the control storage cache 20 including the RAM 11 is backed up by the external control storage 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram-controlled one-chip microprocessor using VLSI. 2゜ [Conventional technology] Conventional microprocessor controlled by microprogram.

In other words, it is used to store microprograms.

A read-only memory (hereinafter referred to as ROM) has been formed on the same chip as a microprocessor to speed up access 5. Also a rewritable memo.

Compared to RAM (hereinafter referred to as RAM), ROM has the advantage that it occupies a smaller area on the chip for the same memory capacity. However, if the contents of the ROM are to be changed, the entire chip must be rebuilt, which is a drawback.・Recent microprocessors are becoming more sophisticated and more functional.

Durham has double track and micro program capacity.

It tends to increase. In this situation, the number of microprogram changes on the chip also increases.

The area of the ROM has also increased, and in the conventional technology, the area of the ROM has increased.

Manufacturing microprocessors is becoming difficult.

Ru.

Cape outside the chip to solve such problems.

I can think of a way to connect the memory, but it's off-chip.

There is an increase in access time due to connecting to.

This results in a decrease in performance. Also, the signal bits required for the chip.

The number of instructions increases and microinstructions with longer bit lengths are created.

Boating is difficult.

JP-A-60-186934 discloses a control memory in a chip.

A method is disclosed in which a microprogram is loaded into the RAM of the chip when the power is turned on, but the control/memory R in the chip is
The capacity limit of AM is more severe than that of ROM, and it is impossible to increase the capacity of many microprograms.

[Problem that the invention seeks to solve]

The conventional technology has the above-mentioned problems.

The object of the present invention is a one-chip microprocessor.

The aim was to increase the capacity of the microprogram by 1° without incurring performance deterioration or manufacturing difficulties.

be.

[Means for solving problems]

The above purpose is to place the minimum necessary control memory ROM on the chip to satisfy performance, and compare it with the microprogram capacity stored outside of this ROM2.

By forming a control unit on the same chip to be used as a cache memory for large-capacity control memory, and accessing the external control memory connected outside the chip at high speed via the cache memory as a backup for the microprogram. achieved.゛〔Operation〕 Due to the high functionality of microprocessors, command words)・Mo1
There are very few cases where the number exceeds 300 to 50.
It becomes necessary to support 0 instruction words. .

But in a program that is processed by a computer.

If you look at the frequency of the instructions that appear, you will find that load, s.

Frequency of basic commands such as door and branch.

are extremely high, and the top 20 instructions are listed in descending order of frequency of appearance.

The execution time occupies a degree of the total program time.

It is often 80-90%.

However, for certain application programs.
・ In addition to basic commands, a high frequency of occurrence was also observed.

Sometimes measured. For example, in a C0DOL program, the frequency of decimal operation instructions increases.

In FORTRAN programs, floating point operations are required.

The frequency of orders increases.

In general, every program has a common occurrence frequency.

High-level instructions require relatively little microprogram capacity.

Therefore, the microprogram is not that complicated.

Considering the above characteristics, microprograms with basic instructions that appear frequently in any program 10 and that particularly require high speed are stored in the control memory RO in the chip.
It is desirable to store it in M. In other words, these microprograms have a relatively small capacity, can be written simply, and their operation can be sufficiently confirmed before creating a VLSI+s mask.

Application of infrequently occurring instructions and characteristics.

For instructions that appear frequently in

A character stored in your memory and formed within the chip.

The control unit 2° in the chip can be adjusted as necessary by the
4. Even if it is read out to memory RAM and used, there is a problem with the processor.

performance will not decrease. This is because, for instructions that occur less frequently, a miss occurs in the cache memory and is read from the external control memory.

The impact of the overhead on performance is small, and once instructions that appear frequently in a particular application are read into the cache memory -2 times, they are subsequently read out.

This is because it will be used over and over again, so you can expect an extremely high hit rate.

Furthermore, when a microprogram is allocated to an external control memory, the control memory cache memory is freed up by arranging a group of instructions used exclusively by an application at a group of addresses.

control storage cache.

The memory RAM has a small capacity and the cache control is simple, such as a 10-15 mapping method, and is sufficiently effective.

The results are promising and the amount of hardware required is small.

Finish.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

It is. 1 indicates a microprocessor chip, which includes a control memory ROMlo, a control memory RAMl1. Cache control unit 12. μ-instruction register 131 μm sequencer 1
4. μ-instruction decoder 15 and instruction processing unit.

It consists of 16 pieces. In addition, RAMII and cache system.

Together with the Shinto 12, it is called the control memory cache 20.
An external control memory 2 is connected to the outside of the microprocessor chip 1 via a .mu.m address bus 31 and a data 10 bus 32.

FIG. 2 shows an address map of the memory and space used by the microprogram. All micro addresses.

The space is 8KW and the micro address (oooo)
16° to (07FF) 16 are assigned to basic instructions that appear frequently, are numbered 5, and are stored in the control memory ROMIO in the chip 1.

Ru. (0800)16~(OFF)16 are unused,
(1000) 16.

~(IFFF) 16 is a decimal operation instruction, a floating point operation instruction.

2% rights commands, system control processing and RAS (trust).

It is assigned to the micro 2° program for functions (axiality, availability, serviceability) and is stored in the external control memory 2. Micrometer output by μm sequencer 14.

If the address is within the range of (0000) 16 to (OFF) 16, the control memory ROMIO is enabled and a microinstruction is output from the ROMIO and taken into the μ-instruction register 13. This control storage cache.

20 does not operate at all, and the control memory RAM II is in a disabled state.

Micro address is (1000hs~(IFFF)16
Range of.

If the
1 and the control memory carriage 20 starts operating.
Ru. In the control storage cache control unit 12, data corresponding to the designated microaddress is stored in control storage.

)1. It is searched to see if it exists in the AM 11, and if it does not exist in the control unit/memory RAM 11, the external control memory 21 is searched.
, reads the corresponding data from the control memory RAM II.
Store in. At the same time, data is treated as microinstructions.

It is taken into the μ-instruction register 13. Designated.

The data corresponding to the microaddress is already under control.

If it exists in the memory RA Mll, the external control unit
7. Direct control memory RAM 1 without reading from memory 2.
Microinstruction data is output from 1, and microinstructions can be read out at high speed. .

The capacity of the control memory RAM II is 512 words, and the cache control unit 12 has a capacity of (1000)16 to (IFFF)16.
The area of 4096 words "□" is divided into 8 blocks of 512 words and managed, and any one word in the control memory RAM II has 8 blocks.

The data of one of the blocks can be stored.

Microinstructions that are unlikely to be used simultaneously in one program are grouped into eight blocks and stored in each block as shown in FIG.

This allows for one program execution state.

is expected to have a high hit rate for control memory cache-20, 5
This allows for less overhead in the event of a mishit.

It can be done with less impact on performance.

Note that when there is a miss in the control memory cache 20, the error occurs.

During data transfer from part control memory 2, the micro instruction is executed.

The overhead is minimal if the bit length of the instruction is equal to the bit length of the instruction.

・8・ However, if a sufficient number of bins for the microprocessor chip 1 cannot be secured, it is possible to import the data to the microprocessor chip 1 in multiple batches.

〔Effect of the invention〕

According to the present invention, it is possible to have a large-capacity microprogram even in a microprogram composed of only one chip, and it is possible to have a microprogram with low performance.

It is possible to minimize the lower part of the conventional ``super mini computer, general purpose computer P phase +''.

It becomes possible to realize the desired number of instructions and functions.・

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing an example of a memory map of a microprogram. 1-11...
Chip, 2... External control memory, 10...
Control memory ROM, 11... Control memory RAM,
, 12... Cache control unit, 20... Control storage cache 7. Shiba! Concave figure 2

Claims (1)

[Claims] 1. A microprocessor for microprogram control, comprising a control memory ROM (ROM) that stores a part of the microprogram, and a rewritable memory that stores other parts of the microprogram. (RAM) and a cache control unit that controls the RAM to operate as a cache memory for the microprogram are configured on the same chip, and other parts of the microprogram are external to the chip. A microprocessor characterized by being provided with an external control memory for storing the data as a backup.