JPS636875A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a soft error from being produced by alpha rays by forming a p-n junction semiconductor layer between both the collector layer and SBD portion of an HBT and a substrate. CONSTITUTION:After Si ions are selectively implanted in a semiinsulative GaAs substrate 10 by using a photo resist as a mask, annealing is performed and the Si ions are activated to form an n-type buried layer 9. Then, Be ions are selectively implanted in a position wherein Si ions are implanted by using the photo resist and annealing is performed to activate the Be ions and form a P-type buried layer 8 whereby a p-n junction is formed. The layers 8 and 9 are so formed as to cover at least the n-type collector layer 12 of an HBT 100, an SBD 101 and the connecting portion of the collector layer 12 and the SBD 101 in a planer fashion. Thus, a soft error rate due to alpha rays is reduced as compared with conventional memory cells.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device suitable for countermeasures against α-ray soft errors.

[Conventional technology]

Conventionally, heterojunction bipolar transistors (Heter.

B 1polar transistor, HB T
Proceedings of the GaAs I C Symposium, 1985, IEE, page 99 (GaAs I
Molecular beam epitaxy (Molecular Beam Epitaxy), as seen in IUY 1985t I EEE, P, 99)
An n-type collector layer and a p-type base layer were formed on a semi-insulating GaAs substrate using the am Epit, axy * MB E) method.

After successive crystal growth with the n-type emitter layer, the desired structure was obtained through processes such as electrode processing.

[Problem that the invention seeks to solve]

The inventors used the above-mentioned conventional technology to set bits from 1 to 16,
Static random access memory (1-16K
SRAM) to normal (7) ECL (E m1ttr C
Schottky barrier diode (
When configured with load-switchable memory cells (SDD), several megaelectrons, which are mainly generated by SRAM packages, are
Due to alpha particles of volts (several M e V ), some of the memories held in the memory are erased. The problem of α-ray soft errors is due to the problem of MOS CMe in Si.
Oxide SemiConduct, er) F
As a result of analyzing the causes of SRAM or Si soft errors by ET, the following facts were revealed.

α rays of several MeV emitted from a package or the like stop after reaching an abnormality of several tens of micrometers from the surface, and generate approximately 10 g of electron-hole pairs. Moreover, the rate of generation of charge pairs is higher immediately before the stoppage when energy is lost due to collisions with Ga and As atoms than when the energy is high immediately after the injection, which is the same as in the case of Si (for example, D, S, Yane
y et al. 1. IEEE ED26 No. 11977, pρ
, see 10-16).

That is, most of the charges generated by the α rays are generated within the semi-insulating GaAs substrate on which the semiconductor element is formed. These charge pairs generated within the substrate spread through diffusion, but when they reach the depletion layer between the semi-insulating GaAs substrate and the n-type collector, they are affected by the electric field existing within the depletion layer. , electrons are attracted into the collector layer.

On the other hand, holes are repelled by a potential barrier.

By the way, since the n-type collector layer is a node that holds the memory cell storage potential, in the case of the collector of an off-side transistor, the base potential of the on-side transistor decreases, and the on-transistor turns off. This is the main mechanism of information destruction.Also, since actual memory cells include resistors, SBDs, etc. in addition to transistors, noise current due to alpha rays flows into the parts other than the transistors.
It is also possible that this influences the collector potential of the memory cell transistor.

That is, when applying HBT to actual SRAM.

It has become necessary to take some kind of alpha ray soft error countermeasure.

The purpose of the present invention is to convert semiconductor elements such as HBT into actual SRAMs.
The aim is to prevent soft nips caused by alpha rays when dealing with such problems.

[Means for solving problems]

In the case of an npn-type HBT, the above purpose is to provide a G
Inserting aAs and SBD (Schottky
This was achieved by inserting a semiconductor layer having a p-n junction also below the barrier diode.

Normally, this p-n junction is used in a memory cell by applying a reverse bias. The above p-n junction is formed by Ga by ion implantation method etc.
It may also be selectively formed within the As wafer. Also, p
In the case of an np-type HBT, the n-p junction is reverse biased and inserted between the collector layer and the substrate.

[Effect]

By employing such a configuration, electron-hole pairs formed in the substrate by α rays will not flow into the collector or SBD. That is, electrons are absorbed into the n layer of the pn junction and taken out from the externally formed ffi hole (connected to the n type layer).

On the other hand, some of the holes are repelled by the weak potential barrier between the n-type layer and the semi-insulating substrate, and the - part of the holes are repelled by the weak potential barrier between the n-type layer and the semi-insulating substrate.
It is absorbed into the mold layer and released through an external electrode connected to the two layers. As a result, most of the electron-hole pairs generated within the substrate are extracted to the outside and no longer cause memory cells to malfunction.

〔Example〕

Hereinafter, the present invention will be explained in more detail through Examples.

Example 1 NPN type H using GaAs/AQGaAsA telojunction
An example of forming a memory cell using BT and SBD will be described with reference to FIGS. 1(a) and 1(b).

Si ions are 3 x 1 (
) After ion implantation at a dose of 13.-2, the photoresist was removed, and a layer of SiO
Annealing was performed in an H2 atmosphere for 20 minutes at 0° C. to activate Si ions and form an n-type buried layer 9. Next, 5
After removing i02, Be ions were implanted at an acceleration voltage of 50 keV at a dose of 5 X I O"cm-2, using a photoresist to overlap the areas where Si was selectively implanted, and after removing the photoresist, 5i02 was deposited on 2000 people using the CVD method, and heated at 950°C using the lamp annealing method.
Seven burns for 10 seconds were performed to activate Be ions, form a p-wall buried M8, and form a p-n junction. At this time, the P-wall buried layer 8 and the n-type buried layer 9 are HBTloo
mouth-shaped collector layer 12 (and its extended portion), a Schottky barrier diode (SBD) 101, and
It is formed so as to cover the bonding portion between the collector layer 12 and the 5BDIOI to a minimum in a plane. Furthermore, in order to form control electrodes in each of the p-wall buried layer 8 and the n-type buried layer 9,
Ion implantation was performed to secure that area.

Next, after removing the SiC2, one surface was etched by about 300 people, and the wafer was placed in a preparation room for MBE (molecular beam epitaxy equipment), where the substrate was heated to remove dirt on the wafer surface.

Furthermore, 8,000 undoped GaAs buffer layers (usually a p- layer of ~10+14CII+''3 level) 11 were formed using the MBE crystal growth layer, and 2
6000 people formed an n-type GaAs collector layer 12 containing about X 101 layer cm-3. Next, add 5 Si
The collector layer 13 containing about X 1015cm-3 is
000 layers, and base layer 14 containing 8 x 1018 GII of Be, 2000 layers, and 2 x 10 Si.
18 cm-” containing nuA Q x Ga + −
x As emitter layer (x ~ 0, 3 about 15 to 200
0, n-type GaAsjetF with similar doping level
16 was grown by 3000 people (Fig. 1(a)).

The crystal growth layers 12, 13, 14, 15, and 16 are.

This is a structure that forms a normal HBT, and in addition to the examples shown here, the AQ mixture ratio between the emitter and base may be graded or
There is only one method to increase the speed of HBT using techniques such as grading the Aα crystal ratio by effectively generating an electric field in the base layer! It is also valid in the example.

Next, a CVD film 33 of SiC2 was deposited to a depth of about 3 μm deeper than the buried layer 89 in the substrate in order to isolate the elements by dry etching using a normal process. Further, an emitter electrode 20, a base electrode 21. Collector electrode 22. It was formed using dry processing. SBD has n-collector ff13, gate metal CAM, Ti/
Pt/Au.

or Mo/Au) 24 was formed directly. The resistance connected to the collector layer is Po1y S +
Although it can be formed on the surface using
b,)) are not shown. Also, this resistance is the base layer 14
It can also be formed using Also, the p-wall buried layer 8. A control electrode for the n-type buried WI9 was also formed using dry etching.

Next, a plan view (FIG. 1(C)) and a cross-sectional view (FIG. 1(d)) of a portion of the memory cell show the state of the power supplies 28 and 29 that are applied to the buried 9M80 layer 9.

In the plan view, the P-wall buried layer 8. An n-type buried layer 9 is formed so as to surround the collector part and the SBD part = the coupling part between the collector and the SBD, and the p-type buried layer 8. The n-type buried layer 9 prevents corrosion.

Further, the entire layer 27 formed by MBE is removed, and grooves are dug in a base plate to form an inter-element isolation layer 33.

Also, wirings 1, 2, 3, 4, 5.6 are M o / A u
was used.

By realizing such a memory cell structure, the conventional α-ray soft error rate could be reduced by four orders of magnitude. or.

Since a completely depleted buffer fill was formed between the collector layer 12 and the buried layers 8 and 9, the parasitic capacitance due to the buried layers 8 and 9 increased by 10% or less.

In this embodiment, a pn junction was selectively formed in the substrate as a barrier and absorption layer for electron-hole pairs generated by α rays, but other methods may also be used. For example, after forming an n-type buried layer 9 on the substrate 10 with a thickness of 4,000 layers at the same doping level as the collector M12, and after forming a p-type buried layer 8 with a thickness of 4,000 layers at the same doping level as the base M14, ! 11, 12, 13, 14.15
16 may be formed.

Example 2 In this example, a pn using a two-dimensional electron gas as a base layer
An example in which the present invention is applied to a p-type 2DEG-HBT is shown in FIGS. 2(a) and 2(b).

First, a p-type buried layer 49 and an n-type buried layer N48 were selectively formed in the semi-insulating GaAs-based Fi10.

That is, a focused ion beam (focused ion beam)
Beam Method)
After selective ion implantation at a dose of 8 x 1013 cm-2 at an accelerating voltage of 00 ksV, lamp annealing was performed at 1000°C for 5 seconds in an N2 atmosphere to activate Be and form a p-type buried layer 49.

Subsequently, Si ions were similarly implanted using the focused ion beam method at an acceleration voltage of 70 keV and a dose of 3 x 10" am-2, and lamp annealing was performed at 900° C. for 15 seconds to form the n-type buried layer 48. Formed.

Next, the wafer is moved in an ultra-high vacuum.

Undoped Ga As layer 51.5 using MBE method
2 was grown to 2 μm. At this time, these layers are usually 51°5
2 is a P- layer of 1014c+n-' or less. However, depending on the purpose, it is also possible to change 51 to an n-layer and 52 to a p-layer. Furthermore, with the focused ion beam method, B
Acceleration voltage 50 keV, dose 8X 1013e1
m-2 was implanted, and flash annealing was performed at 850° C. for 10 seconds. Next, it was returned to the MBE chamber once again, and 2500 p-GaAs53 containing 3 x 10 cm-' of Be was grown, and furthermore, 2 x 10 cm of Si was grown.
cm-” containing n-type A Q O,3Ga o,t A
500 layers of sH25, 300 layers of AQn, 3Ga n, 7As layer 56 containing 5X 10"cm-3 of Be.
0 people, 300 GaAs layers 57 containing the same amount of Be.
0 people were formed (Figure 2 (a)).

Subsequently, a base electrode 61, a collector electrode 62, and an emitter electrode 60p-type G a A were formed using a method similar to Example 1.
A Schottky contact 64 to the s-layer 53 was formed. For isolation between elements, a grooved isolation layer 33 was used in the same manner as in Example 1.

In this transistor, the base layer is n-type AuGaAs
It is formed by a two-dimensional electron gas formed between layer 55 and p-GaAs layer 53.

The p-n junction between the emitter 56 and the n-type AQGaAs layer 55, which is a two-dimensional electron supply layer forming the base layer, is as follows:
The film thickness and doping level are set so that no neutral region remains in the n-type AQGaAs layer.

The reason why the order of p-n junctions is reversed from that in Example 1 is that p
It is an np2DEG-HBT, and this is due to the fact that the roles of electrons and holes are reversed.

Further, in the same manner as in Example 1, a control electrode for the buried layer was formed. Further, the buried nine layers or n layer can also be formed using a shrimp layer as in the first embodiment.

In this way, since the collector layer and SBD could be protected with the p-n junction buried layer, this memory cell could be used to
When an SRAM was formed, a soft error rate reduction of approximately 5 orders of magnitude compared to the case without a buried layer was achieved. Furthermore, the parasitic capacitance was hardly increased by inserting the depleted buffer layers 51 and 52 between the collector layer 58 and the buried layers 48 and 49.

Although this example is explained using a GaAs/AQGaAs heterojunction, other heterozygous systems, rnP-InGa
AsP, InGaAs/AQ InAs, InP-
InGaAs, GaAs/Ge+ AQGaAs/Ge
It is also effective in heterozygous systems such as

The present invention is effective not only for HBTs but also for homojunction bipolar transistors.

In addition, np (11fJ
Even in a two-dimensional Hall gas-HBT, α-ray soft error countermeasures as shown in this embodiment are effective.

Also, in this example, the case of 2DEC with a single heterojunction was shown, but the 'a'a of 2DEC using a double heterojunction was shown.
It is also possible to approximately double the degree.

〔Effect of the invention〕

According to the present invention, since the collector layer and the Schottky barrier diode portion of the HBT are protected by forming a p-n junction semiconductor layer between them and the substrate, soft errors caused by alpha rays are more likely to occur than in conventional memory cells. The rate could be reduced by about 4 to 5 orders of magnitude/J%. Further, when such a ρ-n junction region is selectively formed on the substrate, the parasitic capacitance between the collector and substrate does not increase.

[Brief explanation of drawings]

FIG. 1 is a sectional view or a plan view showing Example 1 of the present invention. FIG. 2 is a sectional view showing a second embodiment of the present invention. 8.49...P type buried layer, 9,48...N type buried layer, 14,54.55...Base layer, 54...2
Dimensional electron gas, 15...n-type AρGaAs (emitter). 16- n-type Ga As, + 1,5], 52-
...Undoped buffer GaAs, 58...P type G
a As collector layer, 12... N-type GaAs collector layer, 24.64... Schottky'R pole, 20
, 60... Emitter electrode, 22.62... Collector electric field, 21.61... Base electrode, 28.29...
・Control electrode. 33... between elements 6 ・') Agent Patent attorney Katsuma Ogawa, 1 ゝ -- 7th 1a

Claims (1)

[Claims] 1. At least one semiconductor element, and a semiconductor layer having a conductivity type opposite to that of a first semiconductor layer constituting the bottom of the semiconductor element and provided below the first semiconductor layer. It is characterized by comprising a second semiconductor layer and a third semiconductor layer having the same conductivity type as the first semiconductor layer and provided in contact with the lower part of the second semiconductor layer. Semiconductor equipment. 2. The semiconductor device according to claim 1, wherein the semiconductor element is a bipolar transistor, and the first semiconductor layer is a collector layer. 3. Claim 1, wherein the semiconductor element is a Schottky barrier diode (SBD).
1. Semiconductor device described in Section 1. 4. A fourth semiconductor layer having an impurity concentration of 10^1^5 cm^-^3 or less is formed between the first semiconductor layer and the second semiconductor layer. A semiconductor device according to claims 1 to 3. 5. The semiconductor according to claims 1 to 4, wherein an electrode for controlling a carrier is formed on at least one of the second semiconductor layer and the third semiconductor layer. Device. 6. The semiconductor device according to claim 1, wherein the second semiconductor layer and the third semiconductor layer are selectively formed within the substrate.