JPS6367796B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to pay television systems, and in particular to improvements in their encryption systems.

There are two main types of encryption methods used in conventional pay television systems: one is to suppress the synchronization signal component to obtain an encrypted television signal, and the other is to invert the video signal component to encrypt it. Separated.

The former method has advantages such as a simple circuit, low cost, and good image quality because it is usually processed using high frequencies, but it is not suitable for pay television systems because it is less secure against eavesdropping. It has a fatal flaw.

On the other hand, the latter method has higher security against eavesdropping than the former method, but the circuit is complicated, the decoder is expensive, the electrical characteristics of the TV signal deteriorates, a data bus is generated, etc. There are drawbacks.

The present invention has been made to improve the drawbacks of such conventional systems, and is capable of converting encrypted television signals by moving the black level of the video signal component of a normal television signal beyond the pedestal level to the sync signal side. The purpose of the present invention is to provide a new pay television system that is simple in construction and has good safety and image quality.

In the present invention, after a normal television signal is modulated by the encoder on the transmitting side, level suppression processing is performed on both the synchronization signal component and the video signal component, and the black level of the video signal component is adjusted to the pedestal level as described above. , and move it to the synchronizing signal component side to create and transmit a high-frequency encrypted television signal, such as _S1 in FIG. 3, for example. This switching of the suppression level is performed in response to a control code output from a random code generation circuit whose initial state is set in the encoder. At this time, in order to operate the AGC circuit on the receiving side, a normal horizontal synchronization signal without encryption processing is transmitted every three to four horizontal synchronization signals.

Even if this high-frequency encrypted television signal is received by a normal television receiver, a signal like _S4 in FIG. 3 will be detected, and the synchronization will be disrupted, making it impossible to view the signal.

The decoder on the receiving side responds with the same control code as the one on the sending side, which is output from the random code generation circuit in synchronization with the encoder on the sending side, and performs S ₂ in Fig. 3.
By giving the video synchronized re-output signal of
_S3 ) is restored and supplied to the television receiver.

In this case, the subscriber is notified in advance so that the status setting code of the random code generation circuit matches the encoder and decoder.

The present invention will be described below with reference to the embodiments shown in the drawings. In the transmitting device shown in FIG. 1, 1 is a modulator, 2 is a high frequency video synchronization signal processing circuit (encoder), 3 is an exciter, 4 is an antenna, 5 is a random code generation circuit.

The modulator 1 modulates a normal television signal, and the modulated television signal is applied to a high frequency video synchronization signal processing circuit 2, which generates the aforementioned code in response to the control code from the random code generation circuit 5. An encrypted television signal as shown in _S1 in FIG.

Note that the audio signal in the present invention is a 0 to 15KHz audio signal, a pilot signal component of _H , and _3H or _4H as a reference, as shown in Figure 2, and ± on both sides thereof.
It consists of a 15KHz carrier sub-audio signal component.

Figure 4 shows the decoder on the receiving side, 6 is the tuner,
7 is a high frequency amplification circuit, 8 is a video detection circuit, 9 is a
AGC circuit, 10 is a V trigger generation circuit, 11 is an audio detection circuit, 12 is an audio processing circuit, 13 is a low frequency amplifier, 14 is a speaker, 15 is a PLL circuit, 1
6 is a horizontal blanking period pulse generation circuit, 17 is a synchronization pulse generation circuit, 18 is a video pulse generation circuit, 1
9 is a random code generation circuit, 20 is a state setting switch, 21 is a video synchronized reproduction signal synthesis circuit, 22
is a high frequency video synchronization signal processing circuit.

In the decoder of FIG. 4, when the high frequency encrypted television signal _S1 transmitted from the broadcasting station is received,
Added to Chuyuna 6. The tuner 6 converts the received frequency to a required frequency, and applies the frequency conversion output to the high frequency amplifier circuit 7. The encrypted television signal amplified by the circuit is detected by the video detection circuit 8, and a part of the detection output is
AGC is applied to the tuner 6 by extracting only the regular horizontal synchronizing signals that are added to the AGC circuit 9 and sent every 3 to 4 from the transmitting side.

Further, the detection output of the video detection circuit 8 is given to a V trigger generation circuit 10 and an audio detection circuit 11. The detected output is given to the audio processing circuit 12, and the output processed by the circuit is amplified by the low frequency amplifier 13 and drives the speaker 14. At this time, a pilot signal _H is extracted from the voice-detected synthesized audio signal and sent to the PLL circuit 15.
This circuit performs phase locking, and its output is added to the audio processing circuit 12 to process the audio detection output.

Now, since the video signal is encrypted as mentioned above, it must be restored to a normal high-frequency television signal.
Since a normal screen is not reproduced, the pilot signal used in audio signal processing is reused as follows. That is, _{the H} output signal of the PLL circuit 15 is sent to the horizontal retrace period pulse generation circuit 16 and the synchronization pulse generation circuit 1.
7 and the video pulse generation circuit 18 for processing, and the video synchronous reproduction signal synthesis circuit 2 from each circuit.
1, a horizontal blanking period pulse, a synchronization pulse, and a video pulse are applied. At the same time, the synchronization pulse is also given to the random code generation circuit 19.

The random code generation circuit 19 has its initial state set by the state setting switch 20, and supplies an N-bit random code to the video synchronized reproduction signal synthesis circuit 21 in units of vertical or horizontal retrace lines. In response to this random code, the circuit 21 operates as shown in FIG.
A video synchronization reproduction signal such as S ₂ is output and applied to the high frequency video synchronization processing circuit 22. The circuit 22 restores the high frequency encrypted television signal as shown in S1 in FIG. 3 given from the video detection circuit ₈ , as shown in _S3 in the same figure, and supplies it to the input terminal I of the television receiver.

FIG. 5 shows an example of the configuration of the video synchronized reproduction signal synthesis circuit 21. As shown in FIG. In the figure, 23 to 26 are control code application terminals supplied from the random code generation circuit 19, 27 is a video pulse application terminal, and 2
8 is a horizontal retrace pulse application terminal, 29 is a synchronization pulse application terminal, 30 is a 2 line = 4 line decoder, 32 to 36 are AND gates, 37 is an integration circuit, 38 is a differentiation circuit, 39 to 43 are transmission gates 44 is a negative direction clamp circuit, 45 is a positive direction clamp circuit, and 46 is a video synchronized reproduction signal output terminal.

FIG. 6 shows an example of the configuration of the random code generation circuit 19. In the figure, d ₁ to _{d o} are D-type flip-flop circuits, S is a set terminal, CL is a clock terminal, D ₁ to D _N are random control code output terminals, and SW ₁ to _{SW o-2} are the aforementioned state setting switches. 20
Each switch that makes up the circuit, OR, is an OR circuit.

The flip-flop circuits d ₁ to _{d o} constitute a pseudo-random number generation circuit, and by switching the switches SW ₁ to _{SW o-2} , the random number generation pattern can be changed and the code can be switched.

A vertical trigger pulse or its count N ₁ times is applied to the set terminal S, a sync pulse or its count N ₂ times is applied to the clock terminal CL, and N bits of control are applied to the output terminals D ₁ to _{D N.} The code can be obtained in horizontal or vertical retrace units.

The control code obtained as described above is applied to the terminals 23 to 2 of the video synchronized reproduction signal synthesis circuit 21 in FIG.
6, the decoder 30 and the buffer circuit 3
1, and each output is an AND gate 32~
36 inputs. The video pulse applied to the terminal 27 is applied to the other inputs of the AND gates 32 to 34, the integrating circuit 37, the differentiating circuit 38, and the transmission gate circuit 39, and is also applied to the circuits 37, 3.
The outputs of 8 are applied to transmission gate circuits 40 and 41, respectively. The transmission gate circuits 39 to 41 are controlled by the outputs of AND gates 32 to 34, respectively, and the outputs of the husband's transmission gate circuits are combined and added to the negative direction clamp circuit 44, and the maximum value of the output is clamped. be done.

On the other hand, the horizontal retrace pulse and synchronization pulse applied to terminals 28 and 29 are applied to transmission gates 42 and 43 controlled by the other inputs of AND gates 35 and 36 and the outputs of the AND gates. The outputs are combined and applied to a positive direction clamp circuit 45, where the minimum value of the outputs is clamped.

The signals clamped by the negative direction clamp circuit 44 and the positive direction clamp circuit 45 are combined, and a video synchronized reproduction signal is obtained at a terminal 46.

FIG. 7a shows an example of the transmission gate circuits 39 to 43, in which Tr ₁ and Tr ₂ are transistors. FIGS. 7b and 7c are circuit examples of the clamp circuits 44 and 45, respectively, in which Tr ₃ and Tr ₄ are transistors, and D ₁ and D ₂ are clamp diodes.

FIG. 8 shows an example of the high frequency video synchronizing signal processing circuit 22, in which the FET is a field effect transistor.
High frequency encrypted television signal S ₁ to terminal 47, terminal 48
When the video synchronous playback signal S ₂ is applied to each, the gate input of the FET is clamped to the same level as the video synchronous playback signal.
9, a normal high frequency television signal _S3 is obtained.

FIG. 9 shows a detailed configuration example of the transmitting side system of the present invention shown in FIG. The normal television signal in FIG. 10 obtained from the video signal source 51 in the same figure.
A timing circuit 53 from _S'1 generates timing signals for a horizontal synchronization signal and a vertical synchronization signal. This timing is applied to the random code generation circuit 55, and a random code is generated at the timing of the horizontal synchronization signal. The random code generation circuit 55 sets the state setting by the state setting switch 56. The control code and the timing are applied to an encrypted signal generating circuit 54 to generate an encrypted signal _S'3 . The encrypted signal generation circuit is similar to the video synchronization signal reproduction signal synthesis circuit on the decoder side described above.
The encrypted signal _S'3 is obtained by inverting the level of the video synchronization signal reproduction signal with respect to the clamp level. This process is similar to that of the video synchronized reproduction signal synthesis circuit shown in FIG. 5 described above. On the other hand, the television signal obtained from the video signal source 51 is transmitted to the video signal modulator 5.
The modulated television signal S' ₂ obtained in addition to 2 and the encrypted signal obtained from the encrypted signal generation circuit 54 are applied to a high frequency video synchronization signal processing circuit 57, and an encrypted high frequency television signal S' ₄ is obtained. . The high frequency video synchronization signal processing circuit 57 is the same as the high frequency video synchronization signal processing circuit of the decoder described above.

As for the audio signal, a pilot signal of 15,734 KHz is obtained from a pilot signal generation circuit 58 based on a timing signal obtained from a timing generation circuit 53. The audio signal source 59 is an encrypted audio signal, which is applied to a modulation circuit 60 and modulated with a _3H or _4H carrier. The audio signal source 61 is an unencrypted audio signal. The pilot signal, the encrypted signal, and the audio signal are transmitted to the audio modulation circuit 6.
2 and is modulated at high frequency. The frequency spectrum of the audio signal in the baseband is as shown in FIG. The encrypted high-frequency signal obtained from the high-frequency video synchronization signal processing circuit 57 and the audio high-frequency signal obtained from the audio modulator 62 are frequency-converted and amplified by an exciter 63.
Emitted from 4.

As described above, in the encryption processing method of the present invention, the black level of the video signal component of a normal television signal is moved beyond the pedestal level to the sync signal side, but the level shift in this case is performed using a triangular wave, a rectangular wave, It can be done so that it has a shape such as a curve. It goes without saying that the size and shape of the level can be changed randomly.

As is clear from the above explanation, the present invention can exhibit excellent effects as described below.

(1) Since encrypted television signals are processed at high frequencies, there is little deterioration in image quality, and the device configuration is simple and inexpensive.

(2) Since the level of the synchronization signal is switched randomly, it has high scrambling properties.

(3) It has a high degree of security because the levels of the video signal components are randomly transformed and switched. Even if the synchronization signal were to be restored with the intention of eavesdropping, it would be difficult to know the contents.

(4) No code is superimposed on the encrypted television signal as in the past, so data buses etc. do not occur. Furthermore, even if you intend to steal a video, it will not give any clues to deciphering it.

[Brief explanation of drawings]

1 and 4 are block diagrams showing the configuration of a transmitting side and receiving side system according to an embodiment of the present invention, and FIG. 2 is a diagram showing the frequency spectrum of an audio signal.
FIG. 3 is a waveform diagram for explaining the method for restoring an encrypted television signal according to the present invention, and FIGS. 5 and 9 show an example of the configuration of a video synchronized reproduction signal synthesis circuit and a transmission side system in the above embodiment. block diagram,
6 is a block diagram showing a configuration example of a random code generation circuit, and FIGS. 7a, b, and c are circuits illustrating the transmission gate circuit, negative direction clamp circuit, and positive direction clamp circuit, respectively, in FIG. 5. figure,
Similarly, FIG. 8 is a circuit diagram illustrating a high frequency video synchronization signal processing circuit, and FIG. 10 is a waveform diagram for explaining the operation of the system of FIG. 9. 2... High frequency video synchronization signal processing, 5... Random code generation circuit, 6... Tuner, 19... Random code generation circuit, 20... Status setting switch, 21...
Video synchronous reproduction signal synthesis circuit, 22...High frequency video synchronous signal processing circuit.

Claims (1)

[Claims] 1. After modulating a normal television signal, the synchronization signal component and video signal component of the modulated television signal are
A high frequency A pay television system characterized by obtaining an encrypted television signal and transmitting it to the receiving side. 2. The pay television system according to claim 1, wherein the level movement is in the form of a triangular wave, a rectangular wave, a curved line, or the like. 3. A patent characterized in that a random code generation circuit is provided on the receiving side to generate a control code independently and in synchronization with the transmitting side, and the high frequency encrypted television signal is restored to a normal television signal by the control code. A pay television system according to claim 1.